Inventor

KELKAR AMIT S

US18 patents

⚠️ This page may combine multiple inventors who share the name “KELKAR AMIT S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KELKAR AMIT S

MAXIM INTEGRATED PRODUCTS

Wafer-level passive device integration

Fan-out and heterogeneous packaging of electronic components

Wafer-level thin chip integration

Warpage compensation metal for wafer level packaging technology

Semiconductor device having a buffer material and stiffener

Bonded stacked wafers and methods of electroplating bonded stacked wafers

Three-dimensional chip-to-wafer integration

Technique for wafer-level processing of QFN packages

Wafer-level package device having high-standoff peripheral solder bumps

Method for varied topographic MEMS cap process

ATMEL CORP

Method for depositing a selected thickness of an interlevel dielectric material to achieve optimum global planarity on a semiconductor wafer

Method of forming pre-metal dielectric film on a semiconductor substrate including first layer of undoped oxide of high ozone:TEOS volume ratio and second layer of low ozone doped BPSG

Method of forming shallow trench isolation structure in a semiconductor device

Method for fabrication of a high capacitance interpoly dielectric

Method of forming pre-metal dielectric film on a semiconductor substrate including first layer of undoped oxide of high ozone:TEOS volume ratio and second layer of low ozone doped BPSG

Method for fabrication of a high capacitance interpoly dielectric

ZOU QUANBO

Bonded stacked wafers and methods of electroplating bonded stacked wafers

KELKAR AMIT S

Thermal processing of silicon wafers