Inventor

DUBUQUE JOHN P

US26 patents

⚠️ This page may combine multiple inventors who share the name “DUBUQUE JOHN P”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DUBUQUE JOHN P

IBM

Method and system for evaluating statistical sensitivity credit in path-based hybrid multi-corner static timing analysis

Modeling multi-patterning variability with statistical timing

Hierarchical design of integrated circuits with multi-patterning requirements

Reducing runtime and memory requirements of static timing analysis

Parasitic extraction in an integrated circuit with multi-patterning requirements

Methods for identifying failing timing requirements in a digital design

Variable threshold system and method for multi-corner static timing analysis

Estimation of process variation impact of slack in multi-corner path-based static timing analysis

Modeling multi-patterning variability with statistical timing

Method to identify timing violations outside of manufacturing specification limits

Partial parameters and projection thereof included within statistical timing analysis

Modeling multi-patterning variability with statistical timing

Hierarchical design of integrated circuits with multi-patterning requirements

Method and system for analyzing cross-talk coupling noise events in block-based statistical static timing

Parameter ordering for multi-corner static timing analysis

Integrating manufacturing feedback into integrated circuit structure design

Parasitic extraction in an integrated circuit with multi-patterning requirements

Partial parameters and projection thereof included within statistical timing analysis

BUCK NATHAN C

Method, system and program storage device for performing a parameterized statistical static timing analysis (SSTA) of an integrated circuit taking into account setup and hold margin interdependence

Timing closure on multiple selective corners in a single statistical timing run

Method for modeling variation in a feedback loop of a phase-locked loop

Integrating manufacturing feedback into integrated circuit structure design

System and method for efficient modeling of NPskew effects on static timing tests

GLOBALFOUNDRIES INC

Dynamic and adaptive timing sensitivity during static timing analysis using look-up table

DUBUQUE JOHN P

Statistical single library including on chip variation for rapid timing and power analysis

BUCK NATHAN

Statistical clock cycle computation