P

Inventor

MAGDO INGRID E

US28 patents

Patents

28 patents
US4256532AMar 17, 1981

Method for making a silicon mask

IBM55 citations96
US4359816ANov 23, 1982

Self-aligned metal process for field effect transistor integrated circuits

IBM61 citations95
US3954523AMay 4, 1976

Process for fabricating devices having dielectric isolation utilizing anodic treatment and selective oxidation

IBM60 citations95
US4758528AJul 19, 1988

Self-aligned metal process for integrated circuit metallization

IBM38 citations92
US4485552ADec 4, 1984

Complementary transistor structure and method for manufacture

IBM27 citations92
US4424621AJan 10, 1984

Method to fabricate stud structure for self-aligned metallization

IBM39 citations92
US4400865AAug 30, 1983

Self-aligned metal process for integrated circuit metallization

IBM46 citations92
US4396933AAug 2, 1983

Dielectrically isolated semiconductor devices

IBM33 citations92
US4357622ANov 2, 1982

Complementary transistor structure

IBM41 citations92
US4023197AMay 10, 1977

Integrated circuit chip carrier and method for forming the same

IBM33 citations92
US3944447AMar 16, 1976

Method for fabrication of integrated circuit structure with full dielectric isolation utilizing selective oxidation

IBM34 citations92
US4805683AFeb 21, 1989

Method for producing a plurality of layers of metallurgy

IBM50 citations87
US4452645AJun 5, 1984

Method of making emitter regions by implantation through a non-monocrystalline layer

IBM24 citations82
US4002511AJan 11, 1977

Method for forming masks comprising silicon nitride and novel mask structures produced thereby

IBM21 citations82
US3995301ANov 30, 1976

Novel integratable Schottky Barrier structure and a method for the fabrication thereof

IBM23 citations82
US4513303AApr 23, 1985

Self-aligned metal field effect transistor integrated circuit

IBM21 citations81
US4322883AApr 6, 1982

Self-aligned metal process for integrated injection logic integrated circuits

IBM25 citations81
US4028717AJun 7, 1977

Field effect transistor having improved threshold stability

IBM17 citations81
US4608589AAug 26, 1986

Self-aligned metal structure for integrated circuits

IBM11 citations74
US4534806AAug 13, 1985

Method for manufacturing vertical PNP transistor with shallow emitter

IBM15 citations74
US4261003AApr 7, 1981

Integrated circuit structures with full dielectric isolation and a novel method for fabrication thereof

IBM13 citations74
US4044454AAug 30, 1977

Method for forming integrated circuit regions defined by recessed dielectric isolation

IBM18 citations74
US4005471AJan 25, 1977

Semiconductor resistor having a high value resistance for use in an integrated circuit semiconductor device

IBM15 citations74
US3956527AMay 11, 1976

Dielectrically isolated Schottky Barrier structure and method of forming the same

IBM14 citations74
US4149915AApr 17, 1979

Process for producing defect-free semiconductor devices having overlapping high conductivity impurity regions

IBM10 citations73
US4089712AMay 16, 1978

Epitaxial process for the fabrication of a field effect transistor having improved threshold stability

IBM11 citations72
US4154626AMay 15, 1979

Process of making field effect transistor having improved threshold stability by ion-implantation

IBM8 citations68
US4965652AOct 23, 1990

Dielectric isolation for high density semiconductor devices

IBM4 citations63