Inventor
GEORGE ROBERT T
US20 patents
⚠️ This page may combine multiple inventors who share the name “GEORGE ROBERT T”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
19 patentsUS7562179B2Jul 14, 2009
Maintaining processor resources during architectural events
INTEL CORP30 citations96
US7552255B1Jun 23, 2009
Dynamically partitioning pipeline resources
INTEL CORP59 citations94
US7552254B1Jun 23, 2009
Associating address space identifiers with active contexts
INTEL CORP46 citations92
US6772298B2Aug 3, 2004
Method and apparatus for invalidating a cache line without data return in a multi-node architecture
INTEL CORP24 citations92
US10740249B2Aug 11, 2020
Maintaining processor resources during architectural events
INTEL CORP2 citations84
US10303620B2May 28, 2019
Maintaining processor resources during architectural events
INTEL CORP2 citations84
US8046539B2Oct 25, 2011
Method and apparatus for the synchronization of distributed caches
INTEL CORP9 citations82
US7546422B2Jun 9, 2009
Method and apparatus for the synchronization of distributed caches
INTEL CORP12 citations82
US9507730B2Nov 29, 2016
Maintaining processor resources during architectural events
INTEL CORP2 citations74
US8788790B2Jul 22, 2014
Maintaining processor resources during architectural events
INTEL CORP3 citations74
US7904694B2Mar 8, 2011
Maintaining processor resources during architectural events
INTEL CORP2 citations74
US7162546B2Jan 9, 2007
Reordering unrelated transactions from an ordered interface
INTEL CORP9 citations72
US9996475B2Jun 12, 2018
Maintaining processor resources during architectural events
INTEL CORP0 citations63
US9164918B2Oct 20, 2015
Maintaining processor resources during architectural events
INTEL CORP1 citations63
US9152561B2Oct 6, 2015
Maintaining processor resources during architectural events
INTEL CORP1 citations63
US8806172B2Aug 12, 2014
Maintaining processor resources during architectural evens
INTEL CORP0 citations63
US7899972B2Mar 1, 2011
Maintaining processor resources during architectural events
INTEL CORP0 citations63
US9086958B2Jul 21, 2015
Maintaining processor resources during architectural events
INTEL CORP0 citations59
US9164901B2Oct 20, 2015
Maintaining processor resources during architectural events
INTEL CORP0 citations52