Inventor

POLIZZI SALVATORE

IT30 patents

⚠️ This page may combine multiple inventors who share the name “POLIZZI SALVATORE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

POLIZZI SALVATORE

ST MICROELECTRONICS SRL

Non-volatile memory device architecture, for instance a flash kind, having a serial communication interface

Low-consumption power-on reset circuit for semiconductor memories

Level shifter circuit and associated memory device

Integrated device with multiple reading and/or writing commands

Nonvolatile memory device with double serial/parallel communication interface

Hybrid architecture for realizing a random numbers generator

Circuit and method for reading a memory cell of a non-volatile memory device

Memory device with progressive row reading and related reading method

Row decoder for a non-volatile memory device, and non-volatile memory device

Phase change memory device and method of operation

Nonvolatile memory device with parallel and serial functioning mode and selectable communication protocol

Testing method and device for non-volatile memories having a LPC (low pin count) communication serial interface

Level shifter circuit having two-domain level shifting capability

Memory device outputting read data in a time starting from a rising edge of an external clock that is shorter than that of known devices

Memory device accessible with different communication protocols

Fast page programming architecture and method in a non-volatile memory device with an SPI interface

Driving circuit of an output buffer stage having a high speed and a reduced noise induced on power supply

Uprom memory cells for non-volatile memory devices integrated on semiconductors

Circuit and method for reading a memory cell of a non-volatile memory device

Memory device with progressive row reading and related reading method

Row decoder for a non-volatile memory device, and non-volatile memory device

Phase change memory device and method of operation

Device and method for reading non-volatile memories having at least one pseudo-parallel communication interface

Protection register for a phase-change memory

Row decoder for a non-volatile memory device, having reduced area occupation

Address decoder for a non-volatile memory array using MOS selection transistors

Method of writing a group of data bytes in a memory and memory device

Content addressable memory protection circuit and method

Row decoder circuit for a phase change non-volatile memory device

PERRONI MAURIZIO FRANCESCO

Method of generating an enable signal of a standard memory core and relative memory device