Inventor

WOLRICH GILBERT

US114 patents

⚠️ This page may combine multiple inventors who share the name “WOLRICH GILBERT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WOLRICH GILBERT

INTEL CORP

Microengine for parallel processor architecture

Method and apparatus for gigabit packet assignment for multithreaded packet processing

Parallel multithreaded processor with plural microengines executing multiple threads each microengine having loadable microcode

Arbitrating command requests in a parallel multi-threaded processing system

Register set used in multithreaded parallel processor architecture

Enqueueing entries in a packet queue referencing packets

Mechanism for providing early coherency detection to enable high performance memory updates in a latency sensitive multithreaded environment

Software controlled content addressable memory in a general purpose execution datapath

SRAM controller for parallel processor architecture and method for controlling access to a RAM using read and read/write queues

Mapping requests from a processing unit that uses memory-mapped input-output space

Read lock miss control and queue management

Scratchpad memory

Thread signaling in multi-threaded network processor

Parallel multi-threaded processing

Communication between processors

Handling contiguous memory references in a multi-queue system

Method and apparatus for sharing access to a bus

SRAM controller for parallel processor architecture including address and command queue and arbiter

Read lock miss control and queue management

SDRAM controller for parallel processor architecture

Parallel processor with functional pipeline providing programming engines by supporting multiple contexts and critical section

Scratchpad memory

Memory shared between processing threads

Optimizations to receive packet status from fifo bus

Solving parallel problems employing hardware multi-threading in a parallel processing environment

Scratchpad memory

Scratchpad memory

Thread signaling in multi-threaded processor

High-performance hashing system

Method and apparatus for gigabit packet assignment for multithreaded packet processing

Processor having a dedicated hash unit integrated within

Multithreaded microprocessor with register allocation based on number of active threads

Memory interleaving

Communication between processors

Control mechanisms for enqueue and dequeue operations in a pipelined network processor

Software controlled content addressable memory in a general purpose execution datapath

Microengine for parallel processor architecture

Queue management

Port blocking technique for maintaining receive packet ordering for a multiple ethernet port switch

Memory interleaving

Bus interface with a first-in-first-out memory

Communication between processors

Enqueue operations for multi-buffer packets

Method for memory allocation and management using push/pop apparatus

Processing a data packet

Flow control in a network environment

Memory controller for processor having multiple multithreaded programmable units

Sram controller for parallel processor architecture including a read queue and an order queue for handling requests

Multiprocessor infrastructure for providing flexible bandwidth allocation via multiple instantiations of separate data buses, control buses and support mechanisms

COMPAQ COMPUTER CORP

Distributed packet data with centralized snooping and header processing router