Inventor

CHICKERMANE VIVEK

US56 patents

⚠️ This page may combine multiple inventors who share the name “CHICKERMANE VIVEK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHICKERMANE VIVEK

CADENCE DESIGN SYSTEMS INC

Method and mechanism for implementing electronic designs having power information specifications background

Method and apparatus for low-pin count testing of integrated circuits

Method and apparatus for low-pin count testing of integrated circuits

Method and apparatus to use physical design information to detect IR drop prone test patterns

Low power scan test for integrated circuits

Design-For-testability planner

Scan testing architectures for power-shutoff aware systems

Method and system for improving efficiency of XOR-based test compression using an embedded serializer-deserializer

Testing to prescribe state capture by, and state retrieval from scan registers

Reducing mask data volume with elastic compression

Systems and methods for testing integrated circuit designs

Distributed test compression for integrated circuits

Method and apparatus to detect manufacturing faults in power switches

Verification process for IJTAG based test pattern migration

Method and apparatus for automated extraction of a design for test boundary model from embedded IP cores for hierarchical and three-dimensional interconnect test

Test generation for low power circuits

Method and apparatus to use physical design information to detect IR drop prone test patterns

Method and system for construction of a highly efficient and predictable sequential test decompression logic

Method for using XOR trees for physically efficient scan compression and decompression logic

Method for using sequential decompression logic for VLSI test in a physically efficient construction

3D stacked die testing structure

IP block scan chain construction

Method to improve testability using 2-dimensional exclusive or (XOR) grids

Low-power shift with clock staggering

Method for optimally connecting scan segments in two-dimensional compression chains

SoC top-level XOR compactor design to efficiently test and diagnose multiple identical cores

Systems and methods for testing integrated circuit designs

IC chip test engine

Method and system for improving efficiency of sequential test compression using overscan

Elastic compression-optimizing tester bandwidth with compressed test stimuli using overscan and variable serialization

Devices and methods for test point insertion coverage

Power and scan resource reduction in integrated circuit designs having shift registers

Optimizing core wrappers in an integrated circuit

Compacting test patterns for IJTAG test

Locking mechanism and core wrapping for IP core

Test-point flop sharing with improved testability in a circuit design

Method for dividing testable logic into a two-dimensional grid for physically efficient scan

THIRUNAVUKARASU SENTHIL ARASU

Method and apparatus to use physical design information to detect IR drop prone test patterns

Method and apparatus to use physical design information to detect IR drop prone test patterns

Method and apparatus to use physical design information to detect IR drop prone test patterns

Testing to prescribe state capture by, and state retrieval from scan registers

Method and apparatus to use physical design information to detect IR drop prone test patterns

Method and apparatus to use physical design information to detect IR drop prone test patterns

WANG QI

Method and mechanism for implementing electronic designs having power information specifications background

Method and mechanism for implementing electronic designs having power information specifications background

CHAKRAVADHANULA KRISHNA

Testing state retention logic in low power systems

Fault modeling for state retention logic

CHICKERMANE VIVEK

Method and system for reducing switching activity during scan-load operations

KHURANA RAJESH

Method and system for analyzing test vectors to determine toggle counts

CHAKRAVADHANULA KRISHNA V

System and method for automated synthesis of circuit wrappers