Inventor
DESAI Kishor
US35 patents
⚠️ This page may combine multiple inventors who share the name “DESAI Kishor”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
CISCO TECH INC
13 patentsUS9213152B2Dec 15, 2015
Releasable fiber connector for opto-electronic assemblies
CISCO TECH INC7 citations84
US9031107B2May 12, 2015
Interposer configuration with thermally isolated regions for temperature-sensitive opto-electronic components
CISCO TECH INC5 citations84
US8905632B2Dec 9, 2014
Interposer configuration with thermally isolated regions for temperature-sensitive opto-electronic components
CISCO TECH INC11 citations84
US9235019B2Jan 12, 2016
Self-aligning optical connector assembly
CISCO TECH INC6 citations83
US9274290B2Mar 1, 2016
Coupling light from a waveguide array to single mode fiber array
CISCO TECH INC5 citations73
US9417412B2Aug 16, 2016
Arrangement for placement and alignment of opto-electronic components
CISCO TECH INC2 citations63
US8830466B2Sep 9, 2014
Arrangement for placement and alignment of opto-electronic components
CISCO TECH INC2 citations63
US9435965B2Sep 6, 2016
Single mode fiber array connector for opto-electronic transceivers
CISCO TECH INC2 citations62
US9343450B2May 17, 2016
Wafer scale packaging platform for transceivers
CISCO TECH INC2 citations62
US8876410B2Nov 4, 2014
Self-aligning connectorized fiber array assembly
CISCO TECH INC3 citations62
US9575266B2Feb 21, 2017
Molded glass lid for wafer level packaging of opto-electronic assemblies
CISCO TECH INC0 citations52
US9557499B2Jan 31, 2017
Coupling light from a waveguide array to single mode fiber array
CISCO TECH INC0 citations52
US9052445B2Jun 9, 2015
Molded glass lid for wafer level packaging of opto-electronic assemblies
CISCO TECH INC0 citations52
LSI LOGIC CORP
7 patentsUS6133064AOct 17, 2000
Flip chip ball grid array package with laminated substrate
LSI LOGIC CORP72 citations96
US6586825B1Jul 1, 2003
Dual chip in package with a wire bonded die mounted to a substrate
LSI LOGIC CORP23 citations92
US6518161B1Feb 11, 2003
Method for manufacturing a dual chip in package with a flip chip die mounted on a wire bonded die
LSI LOGIC CORP26 citations92
US7041516B2May 9, 2006
Multi chip module assembly
LSI LOGIC CORP7 citations73
US6858930B2Feb 22, 2005
Multi chip module
LSI LOGIC CORP8 citations73
US6680532B1Jan 20, 2004
Multi chip module
LSI LOGIC CORP6 citations73
US6777314B2Aug 17, 2004
Method of forming electrolytic contact pads including layers of copper, nickel, and gold
LSI LOGIC CORP1 citations52
TESSERA INC
5 patentsUS8378478B2Feb 19, 2013
Enhanced stacked microelectronic assemblies with central contacts and vias connected to the central contacts
TESSERA INC48 citations94
US9508687B2Nov 29, 2016
Low cost hybrid high density package
TESSERA INC4 citations73
US9433100B2Aug 30, 2016
Low-stress TSV design using conductive particles
TESSERA INC3 citations73
US9196581B2Nov 24, 2015
Flow underfill for microelectronic packages
TESSERA INC2 citations63
US9875955B2Jan 23, 2018
Low cost hybrid high density package
TESSERA INC0 citations52