Inventor
STRAIN ROBERT J
US20 patents
⚠️ This page may combine multiple inventors who share the name “STRAIN ROBERT J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
NAT SEMICONDUCTOR CORP
5 patentsUS5729075AMar 17, 1998
Tuneable microelectromechanical system resonator
NAT SEMICONDUCTOR CORP98 citations97
US5912779AJun 15, 1999
Method of reading and writing data on a magnetic medium
NAT SEMICONDUCTOR CORP29 citations92
US5644457AJul 1, 1997
Multiple gap read/write head for data storage devices
NAT SEMICONDUCTOR CORP9 citations73
US5517453AMay 14, 1996
Memory with multiple erase modes
NAT SEMICONDUCTOR CORP15 citations73
US5426539AJun 20, 1995
Multiple gap read/write head for data storage devices
NAT SEMICONDUCTOR CORP6 citations73
TOWER SEMICONDUCTOR LTD
4 patentsUS6590797B1Jul 8, 2003
Multi-bit programmable memory cell having multiple anti-fuse elements
TOWER SEMICONDUCTOR LTD32 citations90
US7544557B2Jun 9, 2009
Gate defined Schottky diode
TOWER SEMICONDUCTOR LTD18 citations82
US6809948B2Oct 26, 2004
Mask programmable read-only memory (ROM) cell
TOWER SEMICONDUCTOR LTD13 citations81
US7485941B2Feb 3, 2009
Cobalt silicide schottky diode on isolated well
TOWER SEMICONDUCTOR LTD4 citations61
FAIRCHILD SEMICONDUCTOR
3 patentsUS4585299AApr 29, 1986
Process for fabricating optical wave-guiding components and components made by the process
FAIRCHILD SEMICONDUCTOR42 citations92
US4728998AMar 1, 1988
CMOS circuit having a reduced tendency to latch
FAIRCHILD SEMICONDUCTOR10 citations73
US4603471AAug 5, 1986
Method for making a CMOS circuit having a reduced tendency to latch by controlling the band-gap of source and drain regions
FAIRCHILD SEMICONDUCTOR17 citations73