P

Inventor

OLNOWICH HOWARD THOMAS

US29 patents

Patents

29 patents
US6243378B1Jun 5, 2001

Method and apparatus for minimizing contention losses in networks

IBM122 citations99
US6092155AJul 18, 2000

Cache coherent network adapter for scalable shared memory processing systems

IBM135 citations99
US6044438AMar 28, 2000

Memory controller for controlling memory accesses across networks in distributed shared memory processing systems

IBM210 citations99
US6823429B1Nov 23, 2004

Memory controller for controlling memory accesses across networks in distributed shared memory processing systems

IBM74 citations98
US6072781AJun 6, 2000

Multi-tasking adapter for parallel network applications

IBM233 citations98
US6044059AMar 28, 2000

Method and apparatus for minimizing contention losses in networks

IBM115 citations98
US6408341B1Jun 18, 2002

Multi-tasking adapter for parallel network applications

IBM85 citations97
US6034956AMar 7, 2000

Method of simultaneously attempting parallel path connections in a multi-stage interconnection network

IBM175 citations97
US5774067AJun 30, 1998

Flash-flooding multi-stage interconnection network with parallel path seeking switching elements

IBM133 citations97
US5734826AMar 31, 1998

Variable cyclic redundancy coding method and apparatus for use in a multistage network

IBM183 citations97
US6343346B1Jan 29, 2002

Cache coherent network adapter for scalable shared memory processing systems

IBM54 citations96
US6122674ASep 19, 2000

Bi-directional network adapter for interfacing local node of shared memory parallel processing system to multi-stage switching network for communications with remote node

IBM79 citations96
US6122659ASep 19, 2000

Memory controller for controlling memory accesses across networks in distributed shared memory processing systems

IBM37 citations96
US5774698AJun 30, 1998

Multi-media serial line switching adapter for parallel networks and heterogeneous and homologous computer system

IBM70 citations96
US6263374B1Jul 17, 2001

Apparatus for coupling a bus-based architecture to a switch network

IBM101 citations95
US6215412B1Apr 10, 2001

All-node switch-an unclocked, unbuffered, asynchronous switching apparatus

IBM62 citations95
US5680402AOct 21, 1997

Priority broadcast and multi-cast for unbuffered multi-stage networks

IBM55 citations93
US6389476B1May 14, 2002

Networks adapters for multi-speed transmissions

IBM28 citations92
US6098123AAug 1, 2000

Method and apparatus for dynamic allocation of bandwidth to/from network adapter memory amongst active input/output ports

IBM50 citations92
US5901291AMay 4, 1999

Method and apparatus for maintaining message order in multi-user FIFO stacks

IBM33 citations92
US5835024ANov 10, 1998

Multi-stage interconnection network with selectable function switching apparatus

IBM19 citations92
US5654695AAug 5, 1997

Multi-function network

IBM89 citations92
US5920704AJul 6, 1999

Dynamic routing switch apparatus with clocked signal regeneration

IBM33 citations91
US5786771AJul 28, 1998

Selectable checking of message destinations in a switched parallel network

IBM22 citations91
US5922063AJul 13, 1999

Automatic hardware message header generator

IBM23 citations90
US5742761AApr 21, 1998

Apparatus for adapting message protocols for a switch network and a bus

IBM26 citations90
US6047113AApr 4, 2000

Network adapters for multi-speed transmissions

IBM13 citations74
US5933428AAug 3, 1999

Two-tailed adapter for scalable, non-blocking networks

IBM7 citations74
US6226683B1May 1, 2001

Increasing probability multi-stage network

IBM3 citations61