Inventor

CHINYA GAUTHAM N

US29 patents

⚠️ This page may combine multiple inventors who share the name “CHINYA GAUTHAM N”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHINYA GAUTHAM N

INTEL CORP

Primitives to enhance thread-level speculation

Mechanism for monitoring instruction set based thread execution on a plurality of instruction sequencers

Mechanism to emulate user-level multithreading on an OS-sequestered sequencer

Sequencer address management

Providing hardware support for shared virtual memory between local and remote physical memory

Temporally encoding a static spatial image

Supporting learned branch predictors

Technique for using memory attributes

Device-to-device communication for resource sharing

Reducing microprocessor power with minimal performance impact by dynamically adapting runtime operating configurations using machine learning

Mechanism to schedule threads on OS-sequestered sequencers without operating system intervention

Mechanism for instruction set based thread execution on a plurality of instruction sequencers

Arithmetic logic unit with normal and accelerated performance modes using differing numbers of computational circuits

Prefetcher for delinquent irregular loads

Device-to-device communication for resource sharing

Method and apparatus for dynamically offloading execution of machine code in an application to a virtual machine

Hardware-assisted virtualization for implementing secure video output path

Multi-stage image super-resolution with reference merging using personalized dictionaries

Migration of trusted security attributes to a security engine co-processor

Synchronization of interrupt processing to reduce power consumption

HANKINS RICHARD A

Structured exception handling for application-managed thread units

Mechanism for monitoring instruction set based thread execution on a plurality of instruction sequencers

Mechanism to schedule threads on OS-sequestered sequencers without operating system intervention

Data structure and management techniques for local user-level thread data

JACOBSON QUINN A

Primitives to enhance thread-level speculation

Technique for using memory attributes

CHINYA GAUTHAM N

Providing hardware support for shared virtual memory between local and remote physical memory

NEWBURN CHRIS J

Technique for context state management to reduce save and restore operations between a memory and a processor using in-use vectors

INTEL IP CORP

Interrupt-vector translation lookaside buffer