Inventor
GRIBELYUK MICHAEL A
US27 patents
⚠️ This page may combine multiple inventors who share the name “GRIBELYUK MICHAEL A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
18 patentsUS6982230B2Jan 3, 2006
Deposition of hafnium oxide and/or zirconium oxide and fabrication of passivated electronic structures
IBM112 citations98
US6511876B2Jan 28, 2003
High mobility FETS using A1203 as a gate oxide
IBM84 citations98
US7071103B2Jul 4, 2006
Chemical treatment to retard diffusion in a semiconductor overlayer
IBM120 citations97
US7279413B2Oct 9, 2007
High-temperature stable gate structure with metallic electrode
IBM53 citations96
US6991979B2Jan 31, 2006
Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETs
IBM52 citations96
US6573197B2Jun 3, 2003
Thermally stable poly-Si/high dielectric constant material interfaces
IBM32 citations92
US7115959B2Oct 3, 2006
Method of forming metal/high-k gate stacks with high mobility
IBM17 citations90
US8383483B2Feb 26, 2013
High performance CMOS circuits, and methods for fabricating same
IBM10 citations84
US7754594B1Jul 13, 2010
Method for tuning the threshold voltage of a metal gate and high-k device
IBM17 citations84
US7683418B2Mar 23, 2010
High-temperature stable gate structure with metallic electrode
IBM10 citations84
US7015469B2Mar 21, 2006
Electron holography method
IBM8 citations74
US7521345B2Apr 21, 2009
High-temperature stable gate structure with metallic electrode
IBM5 citations73
US7091128B2Aug 15, 2006
Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETs
IBM6 citations73
US7776701B2Aug 17, 2010
Metal oxynitride as a pFET material
IBM4 citations63
US7667277B2Feb 23, 2010
TiC as a thermally stable p-metal carbide on high k SiO2 gate stacks
IBM4 citations63
US7436034B2Oct 14, 2008
Metal oxynitride as a pFET material
IBM4 citations63
US7566938B2Jul 28, 2009
Deposition of hafnium oxide and/or zirconium oxide and fabrication of passivated electronic structures
IBM0 citations52
US7232774B2Jun 19, 2007
Polycrystalline silicon layer with nano-grain structure and method of manufacture
IBM0 citations50
WESTERN DIGITAL TECH INC
7 patentsUS12408560B2Sep 2, 2025
Buffer layers and interlayers that promote BiSbx (012) alloy orientation for sot and MRAM devices
WESTERN DIGITAL TECH INC0 citations63
US12567438B2Mar 3, 2026
Magnetic heads having low magnetic coercivity (Hc) and high saturated magnetic flux density (Bs) in ferromagnetic (FM) layer(s) or shield(s) with minimized saturation
WESTERN DIGITAL TECH INC0 citations62
US12176132B2Dec 24, 2024
Highly textured 001 BiSb and materials for making same
WESTERN DIGITAL TECH INC0 citations62
US12125512B2Oct 22, 2024
Doping process to refine grain size for smoother BiSb film surface
WESTERN DIGITAL TECH INC0 citations62
US12106791B2Oct 1, 2024
Doped BiSb (012) or undoped BiSb (001) topological insulator with GeNiFe buffer layer and/or interlayer for SOT based sensor, memory, and storage devices
WESTERN DIGITAL TECH INC0 citations62
US12482588B2Nov 25, 2025
Nitrogen doped oxides for lower bandgap
WESTERN DIGITAL TECH INC0 citations61
US11875827B2Jan 16, 2024
SOT reader using BiSb topological insulator
WESTERN DIGITAL TECH INC0 citations57