P

Inventor

SIMMONS LINCOLN T

US18 patents

Patents

18 patents
US9483350B1Nov 1, 2016

Flash memory codeword architectures

IBM25 citations94
US10884914B2Jan 5, 2021

Regrouping data during relocation to facilitate write amplification reduction

IBM35 citations93
US9857986B2Jan 2, 2018

Wear leveling of a memory array

IBM7 citations84
US9652157B2May 16, 2017

Accelerated non-volatile memory recirculation processing

IBM6 citations84
US9645924B2May 9, 2017

Garbage collection scaling

IBM8 citations83
US9280419B2Mar 8, 2016

Dynamic adjustment of data protection schemes in flash storage systems based on temperature, power off duration and flash age

IBM10 citations83
US9740609B1Aug 22, 2017

Garbage collection techniques for a data storage system

IBM7 citations82
US9298549B2Mar 29, 2016

Read buffer architecture supporting integrated XOR-reconstructed and read-retry for non-volatile random access memory (NVRAM) systems

IBM12 citations82
US10365859B2Jul 30, 2019

Storage array management employing a merged background management process

IBM3 citations73
US10082962B2Sep 25, 2018

Wear leveling of a memory array

IBM4 citations73
US9904607B2Feb 27, 2018

Logical to physical table restoration from stored journal entries

IBM2 citations73
US9811419B2Nov 7, 2017

Validation bits and offsets to represent logical pages split between data containers

IBM2 citations73
US9571128B2Feb 14, 2017

Dynamic adjustment of data protection schemes in flash storage systems based on temperature, power off duration and flash age

IBM2 citations72
US10621051B2Apr 14, 2020

Logical to physical table restoration from stored journal entries

IBM0 citations52
US9971517B2May 15, 2018

Accelerated non-volatile memory recirculation processing

IBM0 citations52
US9946594B2Apr 17, 2018

Validation bits and offsets to represent logical pages split between data containers

IBM0 citations52
US9875153B2Jan 23, 2018

Validation bits and offsets to represent logical pages split between data containers

IBM0 citations52
US10169145B2Jan 1, 2019

Read buffer architecture supporting integrated XOR-reconstructed and read-retry for non-volatile random access memory (NVRAM) systems

IBM0 citations49