Inventor
SRINIVASAN SRIKANTH T
US29 patents
⚠️ This page may combine multiple inventors who share the name “SRINIVASAN SRIKANTH T”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
16 patentsUS6779108B2Aug 17, 2004
Incorporating trigger loads in branch histories for branch prediction
INTEL CORP20 citations92
US6662273B1Dec 9, 2003
Least critical used replacement with critical cache
INTEL CORP28 citations92
US6760816B1Jul 6, 2004
Critical loads guided data prefetching
INTEL CORP17 citations84
US7958336B2Jun 7, 2011
System and method for reservation station load dependency matrix
INTEL CORP17 citations83
US6782469B1Aug 24, 2004
Runtime critical load/data ordering
INTEL CORP6 citations74
US7711932B2May 4, 2010
Scalable rename map table recovery
INTEL CORP6 citations73
US10896141B2Jan 19, 2021
Gather-scatter cache architecture having plurality of tag and data banks and arbiter for single program multiple data (SPMD) processor
INTEL CORP3 citations68
US10418098B2Sep 17, 2019
Methods and systems for performing a calculation across a memory array
INTEL CORP1 citations62
US11188341B2Nov 30, 2021
System, apparatus and method for symbolic store address generation for data-parallel processor
INTEL CORP0 citations61
US11243775B2Feb 8, 2022
System, apparatus and method for program order queue (POQ) to manage data dependencies in processor having multiple instruction queues
INTEL CORP1 citations60
US7363477B2Apr 22, 2008
Method and apparatus to reduce misprediction penalty by exploiting exact convergence
INTEL CORP4 citations56
US7487337B2Feb 3, 2009
Back-end renaming in a continual flow processor pipeline
INTEL CORP1 citations52
US7900023B2Mar 1, 2011
Technique to enable store forwarding during long latency instruction execution
INTEL CORP0 citations51
US9495159B2Nov 15, 2016
Two level re-order buffer
INTEL CORP0 citations49
US9904553B2Feb 27, 2018
Method and apparatus for implementing dynamic portbinding within a reservation station
INTEL CORP0 citations46
US9372698B2Jun 21, 2016
Method and apparatus for implementing dynamic portbinding within a reservation station
INTEL CORP1 citations46
AKKARY HAITHAM
4 patentsUS8627030B2Jan 7, 2014
Late lock acquire mechanism for hardware lock elision (HLE)
AKKARY HAITHAM7 citations83
US8190859B2May 29, 2012
Critical section detection and prediction mechanism for hardware lock elision
AKKARY HAITHAM15 citations83
US9798590B2Oct 24, 2017
Post-retire scheme for tracking tentative accesses during transactional execution
AKKARY HAITHAM2 citations72
US9262173B2Feb 16, 2016
Critical section detection and prediction mechanism for hardware lock elision
AKKARY HAITHAM1 citations51