Inventor

CHU WEN-TING

TW249 patents

⚠️ This page may combine multiple inventors who share the name “CHU WEN-TING”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHU WEN-TING

TAIWAN SEMICONDUCTOR MFG CO LTD

Switching layer scheme to enhance RRAM performance

Series MIM structures compatible with RRAM process

Bottom electrode for RRAM structure

Top electrode blocking layer for RRAM device

Embedded ferroelectric memory cell

Perpendicular magnetic tunneling junction (MTJ) for improved magnetoresistive random-access memory (MRAM) process

Metal landing on top electrode of RRAM

Resistive random access memory device

RRAM cell with PMOS access transistor

RRAM device with data storage layer having increased height

RRAM device

Resistive random access memory (RRAM) and method of making

RRAM cell structure with laterally offset BEVA/TEVA

RRAM cell with bottom electrode

Embedded ferroelectric memory cell

Switching layer scheme to enhance RRAM performance

Method for manufacturing memory device having spacer

Metal landing on top electrode of RRAM

Resistive random access memory device

Switching layer scheme to enhance RRAM performance

Resistive random access memory device

Electrode structure to improve RRAM performance

Switching layer scheme to enhance RRAM performance

RRAM memory cell with multiple filaments

TAIWAN SEMICONDUCTOR MFG

Methods and apparatus for non-volatile memory cells with increased programming efficiency

Method for making deep sub-micron mosfet structures having improved electrical characteristics

Method to fabricate a new structure with multi-self-aligned for split-gate flash

One transistor and one resistive (1T1R) random access memory (RRAM) structure with dual spacers

Logic compatible RRAM structure and process

One transistor and one resistive (1T1R) random access memory (RAM) structure with dual spacers

Resistive random access memory (RRAM) structure and method of making the RRAM structure

Integration process to increase high voltage breakdown performance

Tilt-angle ion implant to improve junction breakdown in flash memory application

Implant method to improve characteristics of high voltage isolation and high voltage breakdown

Using ONO as hard mask to reduce STI oxide loss on low voltage device in flash or EPROM process

Process of forming an EEPROM device having a split gate

Process for forming self-aligned source in flash cell using SiN spacer as hard mask

Method of making the selection gate in a split-gate flash eeprom cell and its structure

Split-gate flash cell

Method of forming a floating gate self-aligned to STI on EEPROM

Structure with protruding source in split-gate flash

Split-gate flash cell

Method to free control tunneling oxide thickness on poly tip of flash

Method to combine high voltage device and salicide process

Vertical split gate field effect transistor (FET) device

Split gate field effect transistor (FET) device employing dielectric barrier layer and method for fabrication thereof

Using NO or N2 O treatment to generate different oxide thicknesses in one oxidation step for single poly non-volatile memory

Flash memory structure with stacking gate formed using damascene-like structure

TU KUO-CHI

Process-compatible decoupling capacitor and method for making the same

MOSEL VITELIC INC

Method of forming memory cell with built-in erasure feature