Inventor

TU KUO-CHI

TW194 patents

⚠️ This page may combine multiple inventors who share the name “TU KUO-CHI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TU KUO-CHI

TAIWAN SEMICONDUCTOR MFG

Method of fabricating an embedded DRAM for metal-insulator-metal (MIM) capacitor structure

Metal-insulator-metal capacitors

One transistor and one resistive (1T1R) random access memory (RRAM) structure with dual spacers

Logic compatible RRAM structure and process

One transistor and one resistive (1T1R) random access memory (RAM) structure with dual spacers

Resistive random access memory (RRAM) structure and method of making the RRAM structure

MIM capacitor and metal gate transistor

Metal-insulator-metal capacitors

Structure for reducing leakage currents and high contact resistance for embedded memory and method for making same

Method of manufacturing a capacitor and a metal gate on a semiconductor device

Embedded semiconductor product with dual depth isolation regions

Random access memory (RAM) capacitor in shallow trench isolation with improved electrical isolation to overlying gate electrodes

Self-aligned MIM capacitor process for embedded DRAM

Method for making auto-self-aligned top electrodes for DRAM capacitors with improved capacitor-to-bit-line-contact overlay margin

Structure for capacitor-top-plate to bit-line-contact overlay margin

Method and structure for a top plate design for making capacitor-top-plate to bit-line-contact overlay margin

Embedded DRAM for metal-insulator-metal (MIM) capacitor structure

Method and structure improving isolation between memory cell passing gate and capacitor

Capacitor under bitline (CUB) memory cell structure with reduced parasitic capacitance

Method of fabricating a capacitor under bit line structure for a dynamic random access memory device

Method of fabricating a capacitor under bit line structure with increased capacitance without increasing the aspect ratio for a dry etched bit line contact hole

Resistance variable memory structure and method of forming the same

One transistor and one resistive random access memory (RRAM) structure with spacer

Resistance variable memory structure and method of forming the same

Decoupling MIM capacitor designs for interposers and methods of manufacture thereof

TAIWAN SEMICONDUCTOR MFG CO LTD

Series MIM structures compatible with RRAM process

Top electrode blocking layer for RRAM device

Embedded ferroelectric memory cell

Perpendicular magnetic tunneling junction (MTJ) for improved magnetoresistive random-access memory (MRAM) process

RRAM cell with PMOS access transistor

RRAM device with data storage layer having increased height

Resistive random access memory (RRAM) and method of making

RRAM cell structure with laterally offset BEVA/TEVA

Embedded ferroelectric memory cell

3D RRAM cell structure for reducing forming and set voltages

Semiconductor device including memory and logic circuit having FETs with ferroelectric layer and manufacturing methods thereof

Metal landing method for RRAM technology

Resistance variable memory structure

One transistor and one resistive random access memory (RRAM) structure with spacer

Top electrode for device structures in interconnect

Resistive random access memory (RRAM) structure

Resistance variable memory structure and method of forming the same

Process-compatible decoupling capacitor and method for making the same

Logic compatible RRAM structure and process

Resistive switching random access memory with asymmetric source and drain

Low form voltage resistive random access memory (RRAM)

VANGUARD INT SEMICONDUCT CORP

Global planarization process for high step DRAM devices via use of HF vapor etching

TU KUO-CHI

Process-compatible decoupling capacitor and method for making the same

TZENG KUO-CHYUAN

Method of manufacturing decoupling MIM capacitor designs for interposers

PAI CHIH-YANG

Semiconductor device