Inventor

Liao yu-wen

TW108 patents

⚠️ This page may combine multiple inventors who share the name “Liao yu-wen”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

Liao yu-wen

TAIWAN SEMICONDUCTOR MFG CO LTD

Bottom electrode for RRAM structure

Top electrode blocking layer for RRAM device

Perpendicular magnetic tunneling junction (MTJ) for improved magnetoresistive random-access memory (MRAM) process

RRAM cell with PMOS access transistor

RRAM device with data storage layer having increased height

RRAM device

Resistive random access memory (RRAM) and method of making

RRAM cell structure with laterally offset BEVA/TEVA

RRAM cell with bottom electrode

Method for manufacturing memory device having spacer

RRAM memory cell with multiple filaments

Method for forming a homogeneous bottom electrode via (BEVA) top surface for memory

Memory device having a single bottom electrode layer

Metal landing method for RRAM technology

Bottom electrode for RRAM structure

Resistance variable memory structure

One transistor and one resistive random access memory (RRAM) structure with spacer

Resistive random access memory (RRAM) structure

Top electrode for device structures in interconnect

Resistance variable memory structure and method of forming the same

Logic compatible RRAM structure and process

Resistive switching random access memory with asymmetric source and drain

Low form voltage resistive random access memory (RRAM)

RRAM retention by depositing Ti capping layer before HK HfO

RRAM cell structure with laterally offset BEVA/TEVA

Memory cells breakdown protection

Method for forming a flat bottom electrode via (BEVA) top surface for memory

Integrated circuit and method for fabricating the same

RRAM memory cell with multiple filaments

Interconnect landing method for RRAM technology

Method to form memory cells separated by a void-free dielectric structure

Interconnect landing method for RRAM technology

Top electrode for device structures in interconnect

Memory device

Interconnect landing method for RRAM technology

Memory device and method for fabricating the same

RRAM cell structure with laterally offset BEVA/TEVA

Step height reduction of memory element

RRAM device with data storage layer having increased height

TAIWAN SEMICONDUCTOR MFG

One transistor and one resistive (1T1R) random access memory (RRAM) structure with dual spacers

Logic compatible RRAM structure and process

One transistor and one resistive (1T1R) random access memory (RAM) structure with dual spacers

Resistive random access memory (RRAM) structure and method of making the RRAM structure

Resistance variable memory structure and method of forming the same

One transistor and one resistive random access memory (RRAM) structure with spacer

Resistance variable memory structure and method of forming the same

Low form voltage resistive random access memory (RRAM)

Resistance variable memory structure

Logic compatible RRAM structure and process

Liao yu-wen

Easily taken and carried holder for boots