Inventor

CHEN HSIA-WEI

TW95 patents

⚠️ This page may combine multiple inventors who share the name “CHEN HSIA-WEI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHEN HSIA-WEI

TAIWAN SEMICONDUCTOR MFG CO LTD

Top electrode blocking layer for RRAM device

Perpendicular magnetic tunneling junction (MTJ) for improved magnetoresistive random-access memory (MRAM) process

RRAM cell with PMOS access transistor

RRAM device

Resistive random access memory (RRAM) and method of making

RRAM cell structure with laterally offset BEVA/TEVA

Recap layer scheme to enhance RRAM performance

Method for forming a homogeneous bottom electrode via (BEVA) top surface for memory

Metal landing method for RRAM technology

Resistance variable memory structure

One transistor and one resistive random access memory (RRAM) structure with spacer

Semiconductor structure and method of forming the same

Resistive random access memory (RRAM) structure

Top electrode for device structures in interconnect

Resistance variable memory structure and method of forming the same

Logic compatible RRAM structure and process

Resistive switching random access memory with asymmetric source and drain

Low form voltage resistive random access memory (RRAM)

RRAM cell structure with laterally offset BEVA/TEVA

Memory cells breakdown protection

Method for forming a flat bottom electrode via (BEVA) top surface for memory

Circuit design and layout with high embedded memory density

Threshold voltage-modulated memory device using variable-capacitance and methods of forming the same

Circuit design and layout with high embedded memory density

Interconnect landing method for RRAM technology

Method to form memory cells separated by a void-free dielectric structure

Interconnect landing method for RRAM technology

Top electrode for device structures in interconnect

Semiconductor structure and method of forming the same

Interconnect landing method for RRAM technology

Method for manufacturing semiconductor device

Memory device and method for fabricating the same

RRAM cell structure with laterally offset BEVA/TEVA

Step height reduction of memory element

RRAM cell with PMOS access transistor

Flat bottom electrode via (BEVA) top surface for memory

Method and apparatus for reading RRAM cell

Method and apparatus for reading RRAM cell

TAIWAN SEMICONDUCTOR MFG

One transistor and one resistive (1T1R) random access memory (RRAM) structure with dual spacers

Logic compatible RRAM structure and process

One transistor and one resistive (1T1R) random access memory (RAM) structure with dual spacers

Resistive random access memory (RRAM) structure and method of making the RRAM structure

Resistance variable memory structure and method of forming the same

One transistor and one resistive random access memory (RRAM) structure with spacer

Resistance variable memory structure and method of forming the same

Low form voltage resistive random access memory (RRAM)

Resistance variable memory structure

Logic compatible RRAM structure and process

Resistive random access memory and manufacturing method thereof

Resistive memory cell array with top electrode bit line