Inventor

PHELPS ANDREW E

US37 patents

⚠️ This page may combine multiple inventors who share the name “PHELPS ANDREW E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PHELPS ANDREW E

SUN MICROSYSTEMS INC

Snoop filter for use in multiprocessor computer systems

System and method for determining a global ordering of events using timestamps

Dynamically reconfigurable interconnection

Cage for dynamic attach testing of I/O boards

Method and apparatus for ring buffer flow error detection

Inter-domain data transfer

Victim invalidation

System domain targeted, configurable interconnection

Computer system employing multiple board sets and coherence schemes

System design verification using selected states of a processor-based system to reveal deficiencies

Method and apparatus for providing error isolation in a multi-domain computer system

Method and apparatus for arbitrating transactions between domains in a computer system

Computer system including a memory controller configured to perform pre-fetch operations

CRAY RESEARCH INC

Scalar/vector processor

Partitioned addressing apparatus for vector/scalar registers

Vector/scalar processor with simultaneous processing and instruction cache filling

Method and apparatus for chaining vector instructions

Method and apparatus for separate mark and wait instructions for processors having multiple memory ports

Method of processing a sequence of conditional vector IF statements

Vector processor having registers for control by vector resisters

Method and apparatus for accessing global registers in a multiprocessor system

Method and apparatus for a multiprocessor resource lockout instruction

Method of processing conditional branch instructions in scalar/vector processor

Data processing system for processing one and two parcel instructions

Vector processor having functional unit paths of differing pipeline lengths

SUPERCOMPUTER SYSTEMS LTD

Fast interrupt mechanism for interrupting processors in parallel in a multiprocessor system wherein processors are assigned process ID numbers

Method and apparatus for a special purpose arithmetic boolean unit

Dedicated centralized signaling mechanism for selectively signaling devices in a multiprocessor system

Method and apparatus for a multiple request toggling priority system

Global registers for a multiprocessor system

BURROUGHS CORP

Content addressable memory cell with shift capability

Address translation buffer

Shifter circuit

SCIENT COMPUTER SYSTEMS CORP

Bi-directional databus system for supporting superposition of vector and scalar operations in a computer

Linking scalar results directly to scalar operation inputs on a bidirectional databus in a computer which superpositions vector and scalar operations

SUPERCONDUCTOR SYSTEMS LIMITED

Method and apparatus for non-sequential resource access

ORACLE AMERICA INC

Pipeline structure for a shared memory protocol