Inventor

KESSELRING GRANT P

US36 patents

⚠️ This page may combine multiple inventors who share the name “KESSELRING GRANT P”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KESSELRING GRANT P

IBM

Phased locked loop with multiple voltage controlled oscillators

Implementing dynamic phase error correction method and circuit for phase locked loop (PLL)

CMOS output driver using floating wells to prevent leakage current

Charge pump operating voltage range control using dynamic biasing

Efficient differential charge pump with sense and common mode control

Electromigration monitor

Low power amplifier

Multi-mode design and operation for transistor mismatch immunity

Detecting distortion in spread spectrum signals

Implementing compact current mode logic (CML) inductor capacitor (LC) voltage controlled oscillator (VCO) for high-speed data communications

Differential phase-frequency detector

Guard ring monitor

High frequency AC coupled self-biased divider

On-chip spread spectrum synchronization between spread spectrum sources

Higher yielding improved matching reference circuit especially applicable for high speed mixed signal applications and phase locked loops and charge pumps

Programmable sensitivity frequency coincidence detection circuit and method

Using a burn-in operational amplifier for a phased locked loop regulator

Wire capacitor for transmitting AC signals

Differential phase-frequency detector

Phase locked loop with sense amplifier circuitry

Implementing clock receiver with low jitter and enhanced duty cycle

Implementing clock receiver with low jitter and enhanced duty cycle

Variable frequency oscillator with specialized inverter stages

Phase-locked loop update cancellation

Phase locked loop pulse truncation

Efficient differential charge pump with sense and common mode control

Device mismatch mitigation for medium range and beyond distances

Implementing cascade level shifter for analog voltage

Integrated circuit voltage-controlled oscillator with late-stage fabrication tuning

FICKE JOEL T

Implementing screening for single FET compare of physically unclonable function (PUF)

Implementing dual speed level shifter with automatic mode control

Implementing dual speed level shifter with automatic mode control

Implementing phase locked loop (PLL) with enhanced locking capability with a wide range dynamic reference clock

CHERUIYOT KENNEDY K

Implementing integral dynamic voltage sensing and trigger

Control voltage mirror circuit

KESSELRING GRANT P

Programmable duty cycle selection using incremental pulse widths