Inventor

STROM JAMES D

US32 patents

⚠️ This page may combine multiple inventors who share the name “STROM JAMES D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

STROM JAMES D

IBM

Data processing system having four phase clocks generated separately on each processor chip

Phased locked loop with multiple voltage controlled oscillators

Implementing dynamic phase error correction method and circuit for phase locked loop (PLL)

Charge pump operating voltage range control using dynamic biasing

Systems, methods and computer products for traversing schematic hierarchy using a scrolling mechanism

Efficient differential charge pump with sense and common mode control

Electromigration monitor

Low power amplifier

Method and apparatus for biasing body voltages

Implementing compact current mode logic (CML) inductor capacitor (LC) voltage controlled oscillator (VCO) for high-speed data communications

Differential phase-frequency detector

Voltage controlled oscillator runaway prevention

Guard ring monitor

Wire capacitor for transmitting AC signals

Differential phase-frequency detector

Phase locked loop with sense amplifier circuitry

Implementing clock receiver with low jitter and enhanced duty cycle

Voltage controlled oscillator runaway prevention

Implementing clock receiver with low jitter and enhanced duty cycle

Voltage controlled oscillator runaway prevention

Variable frequency oscillator with specialized inverter stages

Moat construction to reduce noise coupling to a quiet supply

Efficient differential charge pump with sense and common mode control

Implementing cascade level shifter for analog voltage

VCO selection and amplitude management using center tap inductor

Power supply noise insensitive charge pump, loop filter, VCO control, and VCO

FICKE JOEL T

Implementing screening for single FET compare of physically unclonable function (PUF)

Implementing dual speed level shifter with automatic mode control

Implementing dual speed level shifter with automatic mode control

Implementing phase locked loop (PLL) with enhanced locking capability with a wide range dynamic reference clock

CHERUIYOT KENNEDY K

Implementing integral dynamic voltage sensing and trigger

Control voltage mirror circuit