Inventor

YIGZAW THEODROS

US32 patents

⚠️ This page may combine multiple inventors who share the name “YIGZAW THEODROS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

YIGZAW THEODROS

INTEL CORP

Adaptive error correction to improve system memory reliability, availability, and serviceability (RAS)

Method to increase cloud availability and silicon isolation using secure enclaves

Clearing poison status on read accesses to volatile memory regions allocated in non-volatile memory

Read from memory instructions, processors, methods, and systems, that do not take exception on defective data

Apparatus and method for detecting and recovering from data fetch errors

Apparatus and method for detecting and recovering from data fetch errors

Delayed error processing

Adaptive internal error scrubbing and error handling

Device, system, and method to concurrently store multiple PMON counts in a single register

System, apparatus and method for memory mirroring in a buffered memory architecture

Hardware apparatuses and methods to check data storage devices for transient faults

Enabling error status and reporting in a machine check architecture

Handling of error prone cache line slots of memory side cache of multi-level system memory

Interfacing with block-based storage in a processor

Recovery from multiple data errors

Hardware apparatuses and methods to check data storage devices for transient faults

Read from memory instructions, processors, methods, and systems, that do not take exception on defective data

Apparatus and method for system physical address to memory module address translation

Lane based normalized historical error counter view for faulty lane isolation and disambiguation of transient versus persistent errors

Hardware unit for reverse translation in a processor

System and method to increase availability in a multi-level memory configuration

Utilization of non-volatile random access memory for information storage in response to error conditions

Cloud scale server reliability management

Instruction and logic for machine checking communication

YIGZAW THEODROS

Performance prioritization in multi-threaded processors

Injecting a data error into a writeback path to memory

Apparatus and method for implement a multi-level memory hierarchy

Method and apparatus for injecting errors into memory

Apparatus and method for detecting and recovering from data fetch errors

RAJ ASHOK

Mechanism for advanced server machine check recovery and associated system software enhancements

VARGAS JOSE A

Machine check summary register

NACHIMUTHU MURUGASAMY

Secure error handling