Inventor

CHANG JOSEPHINE B

US231 patents

⚠️ This page may combine multiple inventors who share the name “CHANG JOSEPHINE B”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHANG JOSEPHINE B

IBM

Fin field effect transistor devices with self-aligned source and drain regions

Non-replacement gate nanomesh field effect transistor with pad regions

Nanowire mesh device and method of fabricating same

Nanowire mesh device and method of fabricating same

Trilayer josephson junction structure with small air bridge and no interlevel dielectric for superconducting qubits

Selective floating body SRAM cell

Non-replacement gate nanomesh field effect transistor with epitixially grown source and drain

Trilayer Josephson junction structure with small air bridge and no interlevel dielectric for superconducting qubits

Method for fabricating a semiconductor device including gate-to-bulk substrate isolation

Trench silicide with self-aligned contact vias

Integrated etch stop for capped gate and method for manufacturing the same

Diode structure and method for FINFET technologies

Non-replacement gate nanomesh field effect transistor with pad regions

Gate-all-around nanowire field effect transistors

Recessed contact for multi-gate FET optimizing series resistance

Electrode pair fabrication using directed self assembly of diblock copolymers

Suspended superconducting qubits

Fin-last replacement metal gate FinFET

Josephson junctions for improved qubits

Sacrificial layer for channel surface retention and inner spacer formation in stacked-channel FETs

Trilayer Josephson junction structure with small air bridge and no interlevel dielectric for superconducting qubits

Integrated etch stop for capped gate and method for manufacturing the same

III-V, SiGe, or Ge base lateral bipolar transistor and CMOS hybrid technology

Self-aligned pitch split for unidirectional metal wiring

Superconducting airbridge crossover using superconducting sacrificial material

CHANG JOSEPHINE B

Techniques for metal gate workfunction engineering to enable multiple threshold voltage FINFET devices

Fin-last replacement metal gate FinFET process

Hybrid CMOS nanowire mesh device and FINFET device

Nanowire FET and finFET

Bulk FinFET and SOI FinFET hybrid technology

Multiple Vt field-effect transistor devices

Hybrid CMOS nanowire mesh device and PDSOI device

Techniques for gate workfunction engineering to reduce short channel effects in planar CMOS devices

Techniques for metal gate workfunction engineering to enable multiple threshold voltage FINFET devices

Techniques for metal gate work function engineering to enable multiple threshold voltage nanowire FET devices

Fin field effect transistor devices with self-aligned source and drain regions

Raised isolation structure self-aligned to fin structures

Double gate planar field effect transistors

Replacement spacer for tunnel FETs

Asymmetric finFET device with improved parasitic resistance and capacitance

Multiple Vt field-effect transistor devices

BANGSARUNTIP SARUNYA

Replacement gate fin first wire last gate all around devices

Nanowire FET and finFET hybrid technology

Hybrid CMOS technology with nanowire devices and double gated planar devices

Gate-all-around nanowire tunnel field effect transistors

ANDO TAKASHI

FinFET parasitic capacitance reduction using air gap

FinFET parasitic capacitance reduction using air gap

GLOBALFOUNDRIES INC

Electronic device including moat power metallization in trench

Silicided nanowires for nanobridge weak links

ANDERSON BRENT A

Maskless inter-well deep trench isolation structure and methods of manufacture