Inventor
SHENOY SUNIL
US13 patents
Patents
13 patentsUS5604877AFeb 18, 1997
Method and apparatus for resolving return from subroutine instructions in a computer processor
INTEL CORP209 citations98
US5574871ANov 12, 1996
Method and apparatus for implementing a set-associative branch target buffer
INTEL CORP122 citations98
US5812839ASep 22, 1998
Dual prediction branch system having two step of branch recovery process which activated only when mispredicted branch is the oldest instruction in the out-of-order unit
INTEL CORP118 citations97
US5903751AMay 11, 1999
Method and apparatus for implementing a branch target buffer in CISC processor
INTEL CORP38 citations96
US5768576AJun 16, 1998
Method and apparatus for predicting and handling resolving return from subroutine instructions in a computer processor
INTEL CORP75 citations96
US5590368ADec 31, 1996
Method and apparatus for dynamically expanding the pipeline of a microprocessor
INTEL CORP43 citations92
US5944817AAug 31, 1999
Method and apparatus for implementing a set-associative branch target buffer
INTEL CORP27 citations91
US5706492AJan 6, 1998
Method and apparatus for implementing a set-associative branch target buffer
INTEL CORP22 citations91
US5574923ANov 12, 1996
Method and apparatus for performing bi-endian byte and short accesses in a single-endian microprocessor
INTEL CORP37 citations90
US4785428ANov 15, 1988
Programmable memory array control signals
INTEL CORP35 citations88
US5749092AMay 5, 1998
Method and apparatus for using a direct memory access unit and a data cache unit in a microprocessor
INTEL CORP15 citations73
US5313605AMay 17, 1994
High bandwith output hierarchical memory store including a cache, fetch buffer and ROM
INTEL CORP17 citations71
US4821271AApr 11, 1989
Methods and circuits for checking integrated circuit chips having programmable outputs
INTEL CORP5 citations60