Inventor

LEE YAO-SHENG

US75 patents

⚠️ This page may combine multiple inventors who share the name “LEE YAO-SHENG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LEE YAO-SHENG

SANDISK TECHNOLOGIES INC

Methods of fabricating a three-dimensional non-volatile memory device

High aspect ratio memory hole channel contact formation

Multilevel memory stack structure employing support pillar structures

Multilevel memory stack structure with joint electrode having a collar portion and methods for manufacturing the same

Method of making a vertical NAND device using a sacrificial layer with air gap and sequential etching of multilayer stacks

Three dimensional NAND string memory devices with voids enclosed between control gate electrodes

Floating gate ultrahigh density vertical NAND flash memory

Methods of fabricating a three-dimensional non-volatile memory device

Method of making a vertical NAND device using sequential etching of multilayer stacks

Ultrahigh density vertical NAND memory device and method of making thereof

Robust nucleation layers for enhanced fluorine protection and stress reduction in 3D NAND word lines

Molybdenum-containing conductive layers for control gate electrodes in a memory structure

Monolithic three dimensional NAND strings and methods of fabrication thereof

Three-dimensional memory devices containing memory block bridges

Three-dimensional memory device with metal and silicide control gates

Method of making a vertical NAND device using sequential etching of multilayer stacks

Three-dimensional non-volatile memory device

Semiconductor structure with concave blocking dielectric sidewall and method of making thereof by isotropically etching the blocking dielectric layer

Method of making a three-dimensional memory array with etch stop

Method of forming an active area with floating gate negative offset profile in FG NAND memory

Methods of making three dimensional NAND devices

Three dimensional NAND device and method of charge trap layer separation and floating gate formation in the NAND device

Three dimensional vertical NAND device with floating gates

SANDISK TECHNOLOGIES LLC

Three-dimensional memory device with silicided word lines, air gap layers and discrete charge storage elements, and method of making thereof

Three-dimensional memory device containing a lateral source contact and method of making the same

Support pillar structures for leakage reduction in a three-dimensional memory device and methods of making the same

Three-dimensional memory device having direct source contact and metal oxide blocking dielectric and method of making thereof

Support pillar structures for leakage reduction in a three-dimensional memory device

Multi-tier memory device with through-stack peripheral contact via structures and method of making thereof

Three-dimensional cross rail phase change memory device and method of manufacturing the same

Three-dimensional memory devices containing inter-tier dummy memory cells and methods of making the same

Stacked vertical memory array architectures, systems and methods

Three-dimensional memory device with leakage reducing support pillar structures and method of making thereof

Three-dimensional memory device including an inter-tier etch stop layer and method of making the same

Three-dimensional memory device including molybdenum word lines and metal oxide spacers and method of making the same

Bonded assembly containing metal-organic framework bonding dielectric and methods of forming the same

Three-dimensional flat NAND memory device having high mobility channels and methods of making the same

Three-dimensional memory device with thickened word lines in terrace region and method of making thereof

Three-dimensional memory device having multilayer word lines containing selectively grown cobalt or ruthenium and method of making the same

Warpage-compensated bonded structure including a support chip and a three-dimensional memory chip

Warpage-compensated bonded structure including a support chip and a three-dimensional memory chip

Three-dimensional memory device with semicircular metal-semiconductor alloy floating gate electrodes and methods of making thereof

Three-dimensional array device having a metal containing barrier and method of making thereof

ALSMEIER JOHANN

Ultrahigh density vertical NAND memory device and method of making thereof

Ultrahigh density monolithic three dimensional vertical NAND string memory device and method of making thereof

LEE YAO-SHENG

Method of making a three-dimensional memory array with etch stop

Multi-level contact to a 3D memory array and method of making

SANDISK 3D LLC

Memories with cylindrical read/write stacks

PACHAMUTHU JAYAVEL

High aspect ratio memory hole channel contact formation

MAKALA RAGHUVEER S

Three dimensional NAND device and method of charge trap layer separation and floating gate formation in the NAND device