Inventor
LIM CHEE HOW
US28 patents
Patents
28 patentsUS6937075B2Aug 30, 2005
Method and apparatus for reducing lock time in dual charge-pump phase-locked loops
INTEL CORP81 citations97
US6157206ADec 5, 2000
On-chip termination
INTEL CORP221 citations97
US6545522B2Apr 8, 2003
Apparatus and method to provide a single reference component for multiple circuit compensation using digital impedance code shifting
INTEL CORP85 citations96
US6424170B1Jul 23, 2002
Apparatus and method for linear on-die termination in an open drain bus architecture system
INTEL CORP97 citations96
US6411122B1Jun 25, 2002
Apparatus and method for dynamic on-die termination in an open-drain bus architecture system
INTEL CORP101 citations96
US6535047B2Mar 18, 2003
Apparatus and method to use a single reference component in a master-slave configuration for multiple circuit compensation
INTEL CORP53 citations95
US7100060B2Aug 29, 2006
Techniques for utilization of asymmetric secondary processing resources
INTEL CORP50 citations92
US6809606B2Oct 26, 2004
Voltage ID based frequency control for clock generating circuit
INTEL CORP33 citations92
US6771134B2Aug 3, 2004
Frequency control for clock generating circuit
INTEL CORP19 citations92
US6748549B1Jun 8, 2004
Clocking an I/O buffer, having a selectable phase difference from the system clock, to and from a remote I/O buffer clocked in phase with the system clock
INTEL CORP48 citations92
US6717455B2Apr 6, 2004
Apparatus and method to use a single reference component in a master-slave configuration for multiple circuit compensation
INTEL CORP33 citations92
US6326802B1Dec 4, 2001
On-die adaptive arrangements for continuous process, voltage and temperature compensation
INTEL CORP42 citations91
US6919769B2Jul 19, 2005
Method and apparatus for fast lock acquisition in self-biased phase locked loops
INTEL CORP14 citations84
US6924710B2Aug 2, 2005
Voltage ID based frequency control for clock generating circuit
INTEL CORP13 citations83
US6842056B1Jan 11, 2005
Cascaded phase-locked loops
INTEL CORP12 citations83
US6756810B2Jun 29, 2004
Apparatus and method to provide a single reference component for multiple circuit compensation using digital impedance code shifting
INTEL CORP15 citations82
US6351136B1Feb 26, 2002
Passive voltage limiter
INTEL CORP17 citations82
US6509780B1Jan 21, 2003
Circuit compensation technique
INTEL CORP16 citations81
US6522165B2Feb 18, 2003
Bus termination scheme for flexible uni-processor and dual processor platforms
INTEL CORP16 citations79
US6614317B2Sep 2, 2003
Variable lock window for a phase locked loop
INTEL CORP11 citations71
US7257756B2Aug 14, 2007
Digital frequency synthesis clocked circuits
INTEL CORP8 citations66
US7199624B2Apr 3, 2007
Phase locked loop system capable of deskewing
INTEL CORP2 citations63
US7197659B2Mar 27, 2007
Global I/O timing adjustment using calibrated delay elements
INTEL CORP4 citations63
US7184503B2Feb 27, 2007
Multi-loop circuit capable of providing a delayed clock in phase locked loops
INTEL CORP4 citations63
US7023945B2Apr 4, 2006
Method and apparatus for jitter reduction in phase locked loops
INTEL CORP3 citations63
US12156331B2Nov 26, 2024
Technologies for power tunnels on circuit boards
INTEL CORP0 citations53
US11445608B2Sep 13, 2022
Chassis interconnect for an electronic device
INTEL CORP0 citations48
US12396124B2Aug 19, 2025
Fan module interconnect apparatus for electronic devices
INTEL CORP0 citations47