Inventor
PEARCE MARK H
US6 patents
Patents
6 patentsUS6816932B2Nov 9, 2004
Bus precharge during a phase of a clock signal to eliminate idle clock cycle
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US6877085B2Apr 5, 2005
Mechanism for processing speclative LL and SC instructions in a pipelined processor
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US6785152B2Aug 31, 2004
Content addressable memory with power reduction technique
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US6646899B2Nov 11, 2003
Content addressable memory with power reduction technique
BROADCOM CORP11 citations71
US7162613B2Jan 9, 2007
Mechanism for processing speculative LL and SC instructions in a pipelined processor
BROADCOM CORP2 citations62
US7076582B2Jul 11, 2006
Bus precharge during a phase of a clock signal to eliminate idle clock cycle
BROADCOM CORP2 citations62