Inventor
MANUSHAROW MATHEW J
US56 patents
⚠️ This page may combine multiple inventors who share the name “MANUSHAROW MATHEW J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
34 patentsUS9275971B2Mar 1, 2016
Bridge interconnect with air gap in package assembly
INTEL CORP33 citations98
US8866308B2Oct 21, 2014
High density interconnect device and method
INTEL CORP50 citations98
US10847467B2Nov 24, 2020
Power-delivery methods for embedded multi-die interconnect bridges and methods of assembling same
INTEL CORP21 citations94
US10163557B2Dec 25, 2018
Helical plated through-hole package inductor
INTEL CORP6 citations84
US8772924B2Jul 8, 2014
Forming in-situ micro-feature structures with coreless packages
INTEL CORP7 citations83
US12051651B2Jul 30, 2024
Size and efficiency of dies
INTEL CORP2 citations73
US10998120B2May 4, 2021
Method of making an inductor
INTEL CORP1 citations73
US10886228B2Jan 5, 2021
Improving size and efficiency of dies
INTEL CORP1 citations73
US10490503B2Nov 26, 2019
Power-delivery methods for embedded multi-die interconnect bridges and methods of assembling same
INTEL CORP4 citations73
US10446499B2Oct 15, 2019
High density interconnect device and method
INTEL CORP3 citations73
US10085341B2Sep 25, 2018
Direct chip attach using embedded traces
INTEL CORP2 citations73
US9899311B2Feb 20, 2018
Hybrid pitch package with ultra high density interconnect capability
INTEL CORP2 citations73
US9633938B2Apr 25, 2017
Hybrid pitch package with ultra high density interconnect capability
INTEL CORP2 citations73
US10784204B2Sep 22, 2020
Rlink—die to die channel interconnect configurations to improve signaling
INTEL CORP3 citations72
US10186465B2Jan 22, 2019
Package-integrated microchannels
INTEL CORP2 citations72
US10312007B2Jun 4, 2019
Inductor formed in substrate
INTEL CORP3 citations71
US9589866B2Mar 7, 2017
Bridge interconnect with air gap in package assembly
INTEL CORP1 citations63
US9521751B2Dec 13, 2016
Weaved electrical components in a substrate package core
INTEL CORP2 citations63
US12094827B2Sep 17, 2024
Size and efficiency of dies
INTEL CORP0 citations62
US12002745B2Jun 4, 2024
High performance integrated RF passives using dual lithography process
INTEL CORP0 citations62
US11961804B2Apr 16, 2024
Size and efficiency of dies
INTEL CORP0 citations62
US11715695B2Aug 1, 2023
Size and efficiency of dies
INTEL CORP0 citations62
US11608564B2Mar 21, 2023
Helical plated through-hole package inductor
INTEL CORP0 citations62
US11227825B2Jan 18, 2022
High performance integrated RF passives using dual lithography process
INTEL CORP0 citations62
US11158578B2Oct 26, 2021
High density interconnect device and method
INTEL CORP0 citations62
US10971416B2Apr 6, 2021
Package power delivery using plane and shaped vias
INTEL CORP0 citations62
US10410939B2Sep 10, 2019
Package power delivery using plane and shaped vias
INTEL CORP1 citations62
US10522455B2Dec 31, 2019
Integrated circuit package substrate
INTEL CORP0 citations52
US10008451B2Jun 26, 2018
Bridge interconnect with air gap in package assembly
INTEL CORP0 citations52
US9552977B2Jan 24, 2017
Landside stiffening capacitors to enable ultrathin and other low-Z products
INTEL CORP1 citations52
US9214439B2Dec 15, 2015
Forming in-situ micro-feature structures with coreless packages
INTEL CORP0 citations52
US9111916B2Aug 18, 2015
In situ-built pin-grid arrays for coreless substrates, and methods of making same
INTEL CORP0 citations52
US8809124B2Aug 19, 2014
Bumpless build-up layer and laminated core hybrid structures and methods of assembling same
INTEL CORP0 citations51
US7589395B2Sep 15, 2009
Multiple-dice packages using elements between dice to control application of underfill material to reduce void formation
INTEL CORP1 citations51
MANUSHAROW MATHEW J
4 patentsUS8901748B2Dec 2, 2014
Direct external interconnect for embedded interconnect bridge package
MANUSHAROW MATHEW J122 citations97
US8508037B2Aug 13, 2013
Bumpless build-up layer and laminated core hybrid structures and methods of assembling same
MANUSHAROW MATHEW J9 citations82
US9526175B2Dec 20, 2016
Suspended inductor microelectronic structures
MANUSHAROW MATHEW J2 citations62
US10242942B2Mar 26, 2019
Integrated circuit package substrate
MANUSHAROW MATHEW J0 citations51
NALLA RAVI K
4 patentsUS8304913B2Nov 6, 2012
Methods of forming fully embedded bumpless build-up layer packages and structures formed thereby
NALLA RAVI K46 citations97
US8431438B2Apr 30, 2013
Forming in-situ micro-feature structures with coreless packages
NALLA RAVI K17 citations92
US8580616B2Nov 12, 2013
Methods of forming fully embedded bumpless build-up layer packages and structures formed thereby
NALLA RAVI K8 citations83
US8896116B2Nov 25, 2014
Microelectronic package and method of manufacturing same
NALLA RAVI K0 citations51
ROY MIHIR K
2 patentsTAHOE RES LTD
2 patentsCHIU CHIA-PIN
1 patentCHASE HAROLD R
1 patentMALLIK DEBENDRA
1 patentCHASE HAROLD RYAN
1 patentShowing the top 50 of 56 patents by PatentIndex Score.