Inventor

MALLIK DEBENDRA

US140 patents

⚠️ This page may combine multiple inventors who share the name “MALLIK DEBENDRA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MALLIK DEBENDRA

INTEL CORP

Stackable integrated circuit packaging

Lead grid array integrated circuit

Multi-layer molded plastic IC package

Localized high density substrate routing

Methods and apparatuses for providing stacked-die devices

Method of controlling solder ball size of BGA IC components

Power-delivery methods for embedded multi-die interconnect bridges and methods of assembling same

Structure of a thermally and electrically enhanced plastic ball grid array package

Thermally enhanced electronic flip-chip packaging with external-connector-side die and method

Thermally enhanced electronic flip-chip packaging with external-connector-side die and method

Metal ball attachment of heat dissipation devices

Molded substrate stiffener with embedded capacitors

De-coupling capacitor on the top of the silicon die by eutectic flip bonding

Low cost package warpage solution

Localized high density substrate routing

Advance multilayer molded plastic package using mesic technology

An electronic package that has a die coupled to a lead frame by a dielectric tape and a heat sink that providees both an electrical and a thermal path between the die and teh lead frame

Integrated circuit having a two-dimensional lead grid array

Method for attaching and handling conductive spheres to a substrate

Multilayer molded plastic package using mesic technology

Fixture for handling and attaching conductive spheres to a substrate

Microelectronic package with solder array thermal interface material (SA-TIM)

IC package including multi-chip unit with bonded integrated heat spreader

Interconnect architecture with silicon interposer and EMIB

IC package including multi-chip unit with bonded integrated heat spreader

Inorganic-based embedded-die layers for modular semiconductive devices

Low cost package warpage solution

Localized high density substrate routing

Thermally enhanced electronic flip-chip packaging with external-connector-side die and method

Ultra-thin, hyper-density semiconductor packages

Configurable microelectronic package using electrically conductive material

C4 joint reliability

Semiconductor chip package and method of manufacturing same

Microelectronic structures including bridges

Molded substrate stiffener with embedded capacitors

Nested architectures for enhanced heterogeneous integration

IC package including multi-chip unit with bonded integrated heat spreader

Nested architectures for enhanced heterogeneous integration

Localized high density substrate routing

Low cost package warpage solution

Stacked die cavity package

Edge-firing antenna walls built into substrate

MALLIK DEBENDRA

Method of making a multilayer molded plastic IC package

Reduced PTH pad for enabling core routing and substrate layer count reduction

3D integrated circuit package with window interposer

Reduced PTH pad for enabling core routing and substrate layer count reduction

MANUSHAROW MATHEW J

Direct external interconnect for embedded interconnect bridge package

STARKSTON ROBERT

Localized high density substrate routing

ZARBOCK EDWARD A

Photonic package architecture

KARHADE OMKAR G

Methods to form high density through-mold interconnections