Inventor · disambiguated record
Thomas Henry Luedeke
Also filed as: LUEDEKE THOMAS · LUEDEKE THOMAS H · LUEDEKE THOMAS HENRY
21 granted patents·4 pending applications·40 citations·filing 2006–2025
91Inventor score
Top patents by PatentIndex Score
25 records- 0190US9697065B1Systems and methods for managing resetFREESCALE SEMICONDUCTOR INC·Filed 2016·Granted Jul 4, 2017·11 cites·20 claims
- 0284US9448811B2Microprocessor device, and method of managing reset events thereforCULSHAW CARL·Filed 2011·Granted Sep 20, 2016·8 cites·20 claims
- 0376US11144677B2Method and apparatus for digital only secure test mode entryNXP USA INC·Filed 2019·Granted Oct 12, 2021·3 cites·21 claims
- 0475US9712153B1Method and device for reset modification based on system stateFREESCALE SEMICONDUCTOR INC·Filed 2016·Granted Jul 18, 2017·4 cites·17 claims
- 0574US11175723B2System and method of power mode management for a processorNXP USA INC·Filed 2020·Granted Nov 16, 2021·1 cites·13 claims
- 0673US8552764B2Clock glitch detection circuitROHLEDER MICHAEL·Filed 2009·Granted Oct 8, 2013·6 cites·20 claims
- 0767US9781120B2System on chip and method thereforROHLEDER MICHAEL·Filed 2013·Granted Oct 3, 2017·2 cites·12 claims
- 0867US9246478B2Electronic device and method for generating clock signals with and without frequency jitter for one source clock signal generated by a single narrow-band source clock signalLUEDEKE THOMAS HENRY·Filed 2014·Granted Jan 26, 2016·3 cites·20 claims
- 0963US12436552B2Voltage regulator which redundantly monitors for an over-voltage condition based on a regulated voltage provided to a controller and methodsNXP USA INC·Filed 2022·Granted Oct 7, 2025·0 cites·18 claims
- 1063US9024663B2Clock glitch detection circuitROHLEDER MICHAEL·Filed 2013·Granted May 5, 2015·1 cites·20 claims
- 1162US2025383682A1Overclocking detection and responseNXP BV·Filed 2025·Application pending·0 cites
- 1261US12493333B2Power-on-reset request functionality in semiconductor devices and power management ICsNXP USA INC·Filed 2023·Granted Dec 9, 2025·0 cites·14 claims
- 1361US9733952B2Microprocessor, and method of managing reset events thereforLUEDEKE THOMAS·Filed 2012·Granted Aug 15, 2017·1 cites·20 claims
- 1459US12332724B2Processing wakeup requests in a processing system having power management circuitry and a processing circuitryNXP USA INC·Filed 2023·Granted Jun 17, 2025·0 cites·20 claims
- 1554US2025389770A1System and method for area-efficient monitoring of clock signalsNXP BV·Filed 2024·Application pending·0 cites
- 1653US2024411354A1Transitions between low power modes in a processing systemNXP USA INC·Filed 2024·Application pending·0 cites
- 1752US9940140B2Systems and methods of resetting a processorFREESCALE SEMICONDUCTOR INC·Filed 2014·Granted Apr 10, 2018·0 cites·19 claims
- 1851US12126334B2Very low voltage I/O circuit and method for screening defectsNXP USA INC·Filed 2022·Granted Oct 22, 2024·0 cites·11 claims
- 1951US9841795B2Method for resetting an electronic device having independent device domainsCULSHAW CARL·Filed 2014·Granted Dec 12, 2017·0 cites·16 claims
- 2043US8214722B2Method and system for signal error determination and correction in a flexray communication systemLUEDEKE THOMAS·Filed 2006·Granted Jul 3, 2012·0 cites·20 claims
- 2142US8841946B2Electronic circuit, safety critical system, and method for providing a reset signalLUEDEKE THOMAS·Filed 2010·Granted Sep 23, 2014·0 cites·20 claims
- 2241US11047904B2Low power mode testing in an integrated circuitNXP USA INC·Filed 2019·Granted Jun 29, 2021·0 cites·19 claims
- 2341US7958281B2Method and apparatus for transmitting data in a flexray nodeFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Jun 7, 2011·0 cites·19 claims
- 2440US10013327B2Monitor, integrated circuit and method for monitoring an integrated circuitROBERSTON ALISTAIR PAUL·Filed 2013·Granted Jul 3, 2018·0 cites·20 claims
- 2538US2013181696A1Low-voltage exit detector, error detector, low-voltage safe controller, brown-out detection method, and brown-out self-healing methodROHLEDER MICHAEL·Filed 2010·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →