Inventor
ALURKAR SOURABH
US5 patents
Patents
5 patentsUS9916253B2Mar 13, 2018
Method and apparatus for supporting a plurality of load accesses of a cache in a single cycle to maintain throughput
INTEL CORP2 citations70
US12216581B2Feb 4, 2025
System, method, and apparatus for enhanced pointer identification and prefetching
INTEL CORP0 citations58
US11693780B2Jul 4, 2023
System, method, and apparatus for enhanced pointer identification and prefetching
INTEL CORP0 citations58
US11080194B2Aug 3, 2021
System, method, and apparatus for enhanced pointer identification and prefetching
INTEL CORP0 citations58
US10698833B2Jun 30, 2020
Method and apparatus for supporting a plurality of load accesses of a cache in a single cycle to maintain throughput
INTEL CORP0 citations49