Inventor · disambiguated record
Richard W. Doing
Also filed as: DOING RICHARD · DOING RICHARD W · DOING RICHARD WILLIAM
27 granted patents·12 pending applications·671 citations·filing 1997–2022
96Inventor score
Technology areasG06F
Files withIBM24DAVIS GORDON T7MICROSOFT TECHNOLOGY LICENSING LLC4DOING RICHARD WILLIAM2DOING RICHARD W1
Top patents by PatentIndex Score
39 records- 0193US7779232B2Method and apparatus for dynamically managing instruction buffer depths for non-predicted branchesIBM·Filed 2007·Granted Aug 17, 2010·56 cites·20 claims
- 0292US6438671B1Generating partition corresponding real address in partitioned mode supporting systemIBM·Filed 1999·Granted Aug 20, 2002·160 cites·16 claims
- 0391US6018759AThread switch tuning tool for optimal performance in a computer processorIBM·Filed 1997·Granted Jan 25, 2000·180 cites·17 claims
- 0490US7707396B2Data processing system, processor and method of data processing having improved branch target address cacheIBM·Filed 2006·Granted Apr 27, 2010·30 cites·21 claims
- 0588US6993640B2Apparatus for supporting a logically partitioned computer systemIBM·Filed 2004·Granted Jan 31, 2006·44 cites·18 claims
- 0684US8131976B2Tracking effective addresses in an out-of-order processorDOING RICHARD W·Filed 2009·Granted Mar 6, 2012·18 cites·22 claims
- 0782US9715411B2Techniques for mapping logical threads to physical threads in a simultaneous multithreading data processing systemIBM·Filed 2014·Granted Jul 25, 2017·6 cites·20 claims
- 0881US6829684B2Applications of operating mode dependent error signal generation upon real address range checking prior to translationIBM·Filed 2002·Granted Dec 7, 2004·26 cites·14 claims
- 0978US7934081B2Apparatus and method for using branch prediction heuristics for determination of trace formation readinessIBM·Filed 2006·Granted Apr 26, 2011·8 cites·6 claims
- 1078US7836287B2Reducing the fetch time of target instructions of a predicted taken branch instructionIBM·Filed 2008·Granted Nov 16, 2010·7 cites·2 claims
- 1177US7644233B2Apparatus and method for supporting simultaneous storage of trace and standard cache linesIBM·Filed 2006·Granted Jan 5, 2010·8 cites·6 claims
- 1277US6161166AInstruction cache for multithreaded processorIBM·Filed 1999·Granted Dec 12, 2000·83 cites·20 claims
- 1373US7996618B2Apparatus and method for using branch prediction heuristics for determination of trace formation readinessIBM·Filed 2011·Granted Aug 9, 2011·3 cites·12 claims
- 1472US9395992B2Instruction swap for patching problematic instructions in a microprocessorIBM·Filed 2012·Granted Jul 19, 2016·4 cites·19 claims
- 1568US8386712B2Structure for supporting simultaneous storage of trace and standard cache linesIBM·Filed 2008·Granted Feb 26, 2013·4 cites·8 claims
- 1668US7281120B2Apparatus and method for decreasing the latency between an instruction cache and a pipeline processorIBM·Filed 2004·Granted Oct 9, 2007·11 cites·3 claims
- 1767US8127115B2Group formation with multiple taken branches per groupDOING RICHARD WILLIAM·Filed 2009·Granted Feb 28, 2012·6 cites·30 claims
- 1867US7437543B2Reducing the fetch time of target instructions of a predicted taken branch instructionIBM·Filed 2005·Granted Oct 14, 2008·3 cites·2 claims
- 1965US8479184B2General purpose emit for use in value profilingDOING RICHARD WILLIAM·Filed 2010·Granted Jul 2, 2013·2 cites·17 claims
- 2063US12086600B2Branch target buffer with shared target bitsMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2022·Granted Sep 10, 2024·0 cites·18 claims
- 2162US7610449B2Apparatus and method for saving power in a trace cacheIBM·Filed 2006·Granted Oct 27, 2009·2 cites·12 claims
- 2260US7305586B2Accessing and manipulating microprocessor stateIBM·Filed 2003·Granted Dec 4, 2007·7 cites·15 claims
- 2359US7711930B2Apparatus and method for decreasing the latency between instruction cache and a pipeline processorIBM·Filed 2007·Granted May 4, 2010·1 cites·12 claims
- 2455US11487545B2Processor branch prediction circuit employing back-invalidation of prediction cache entries based on decoded branch instructions and related methodsMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2021·Granted Nov 1, 2022·0 cites·20 claims
- 2553US8015565B2Preventing livelocks in processor selection of load requestsIBM·Filed 2005·Granted Sep 6, 2011·1 cites·14 claims
- 2649US2024192957A1Branch target buffer access systems and methodsMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2022·Application pending·0 cites
- 2749US2010262813A1Detecting and Handling Short Forward Branch Conversion CandidatesIBM·Filed 2009·Application pending·0 cites
- 2847US7321954B2Method for software controllable dynamically lockable cache line replacement systemIBM·Filed 2004·Granted Jan 22, 2008·1 cites·12 claims
- 2943US2022283811A1Loop buffering employing loop characteristic prediction in a processor for optimizing loop buffer performanceMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2021·Application pending·0 cites
- 3042US7558948B2Method for providing zero overhead looping using carry chain maskingIBM·Filed 2004·Granted Jul 7, 2009·0 cites·9 claims
- 3142US2008235500A1Structure for instruction cache trace formationDAVIS GORDON T·Filed 2008·Application pending·0 cites
- 3241US2008250206A1Structure for using branch prediction heuristics for determination of trace formation readinessDAVIS GORDON T·Filed 2008·Application pending·0 cites
- 3341US2006155961A1Apparatus and method for reformatting instructions before reaching a dispatch point in a superscalar processorIBM·Filed 2005·Application pending·0 cites
- 3441US2008250207A1Design structure for cache maintenanceDAVIS GORDON T·Filed 2008·Application pending·0 cites
- 3540US2008215804A1Structure for register renaming in a microprocessorDAVIS GORDON T·Filed 2008·Application pending·0 cites
- 3639US2008120468A1Instruction Cache Trace FormationDAVIS GORDON T·Filed 2006·Application pending·0 cites
- 3739US2008077778A1Method and Apparatus for Register Renaming in a MicroprocessorDAVIS GORDON T·Filed 2006·Application pending·0 cites
- 3839US2008114964A1Apparatus and Method for Cache MaintenanceDAVIS GORDON T·Filed 2006·Application pending·0 cites
- 3939US2019294443A1Providing early pipeline optimization of conditional instructions in processor-based systemsQUALCOMM INC·Filed 2018·Application pending·0 cites
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