Inventor

KONIGSBURG BRIAN R

US41 patents

⚠️ This page may combine multiple inventors who share the name “KONIGSBURG BRIAN R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KONIGSBURG BRIAN R

IBM

Distributed memory system with ECC and method of operation

Branch encoding before instruction cache write

Pipelined two-cycle branch target address cache

Instruction group formation and mechanism for SMT dispatch

Method and system for software control of hardware branch prediction mechanism in a data processor

Method and system for speculatively processing a load instruction before completion of a preceding synchronization instruction

System and method for controlling a memory array in an information handling system

Method and system for optimizing the fetching of dispatch groups in a superscalar processor

Support for out-of-order execution of loads and stores in a processor

Data processing system and method for using an unique identifier to maintain an age relationship between executing instructions

Apparatus and method for enforcing data coherency in an information handling system having multiple hierarchical levels of cache memory

In-cycle resource sharing for high-level synthesis of microprocessors

Automating a microarchitecture design exploration environment

Apparatus and method for processing multiple cache misses to a single cache line

Radix sort acceleration using custom asic

Radix sort acceleration using custom ASIC

Method and apparatus for synchronizing parallel pipelines in a superscalar microprocessor

LLVM-based system C compiler for architecture synthesis

Automating a microarchitecture design exploration environment

Techniques for mapping logical threads to physical threads in a simultaneous multithreading data processing system

Predicting indirect branches using problem branch filtering and pattern cache

Simplified method to generate BTAGs in a decode unit of a processing system

Methods and systems for storing branch information in an address table of a processor

Microprocessor instruction fetch unit for processing instruction groups having multiple branch instructions

Radix sort acceleration using custom ASIC

Identifying and tagging breakpoint instructions for facilitation of software debug

Identifying and tagging breakpoint instructions for facilitation of software debug

Fetch-side instruction dispatch group formation

Automating a microarchitecture design exploration environment

Determining each stall reason for each stalled instruction within a group of instructions during a pipeline stall

Storing branch information in an address table of a processor

Adaptive radix external in-place radix sort

Tracking long GHV in high performance out-of-order superscalar processors

KONIGSBURG BRIAN R

Reducing store-hit-loads in an out-of-order processor

Systems and methods for synchronization of processing elements

Storing branch information in an address table of a processor

MICROSOFT TECHNOLOGY LICENSING LLC

Memory system with a content addressable superconducting memory

Memory system with a content addressable superconducting memory

EKANADHAM KATTAMURI

Operating a stack of information in an information handling system

GLOBALFOUNDRIES INC

Techniques for selecting a predicted indirect branch address from global and local caches

INDUKURU VENKAT R

Determining each stall reason for each stalled instruction within a group of instructions during a pipeline stall