Inventor
LEVITAN DAVID STEPHEN
US28 patents
⚠️ This page may combine multiple inventors who share the name “LEVITAN DAVID STEPHEN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
25 patentsUS7487334B2Feb 3, 2009
Branch encoding before instruction cache write
IBM61 citations97
US7269715B2Sep 11, 2007
Instruction grouping history on fetch-side dispatch group formation
IBM62 citations97
US6279105B1Aug 21, 2001
Pipelined two-cycle branch target address cache
IBM62 citations96
US5796758AAug 18, 1998
Self-checking content-addressable memory and method of operation for detecting multiple selected word lines
IBM65 citations96
US7120784B2Oct 10, 2006
Thread-specific branch prediction by logically splitting branch history tables and predicted target address cache in a simultaneous multithreading processing environment
IBM23 citations92
US6662360B1Dec 9, 2003
Method and system for software control of hardware branch prediction mechanism in a data processor
IBM31 citations92
US6651162B1Nov 18, 2003
Recursively accessing a branch target address cache using a target address previously accessed from the branch target address cache
IBM41 citations92
US5872950AFeb 16, 1999
Method and apparatus for managing register renaming including a wraparound array and an indication of rename entry ages
IBM49 citations92
US5758143AMay 26, 1998
Method for updating a branch history table in a processor which resolves multiple branches in a single cycle
IBM43 citations92
US7254700B2Aug 7, 2007
Fencing off instruction buffer until re-circulation of rejected preceding and branch instructions to avoid mispredict flush
IBM14 citations84
US6484256B1Nov 19, 2002
Apparatus and method of branch prediction utilizing a comparison of a branch history table to an aliasing table
IBM20 citations84
US5796998AAug 18, 1998
Apparatus and method for performing branch target address calculation and branch prediciton in parallel in an information handling system
IBM18 citations84
US7890738B2Feb 15, 2011
Method and logical apparatus for managing processing system resource use for speculative execution
IBM8 citations82
US7039768B2May 2, 2006
Cache predictor for simultaneous multi-threaded processor system supporting multiple transactions
IBM10 citations74
US7000233B2Feb 14, 2006
Simultaneous multithread processor with result data delay path to adjust pipeline length for input to respective thread
IBM10 citations74
US5918044AJun 29, 1999
Apparatus and method for instruction fetching using a multi-port instruction cache directory
IBM15 citations74
US5894487AApr 13, 1999
Error detection of directory arrays in dynamic circuits
IBM14 citations74
US6385719B1May 7, 2002
Method and apparatus for synchronizing parallel pipelines in a superscalar microprocessor
IBM12 citations73
US9715411B2Jul 25, 2017
Techniques for mapping logical threads to physical threads in a simultaneous multithreading data processing system
IBM6 citations71
US6304959B1Oct 16, 2001
Simplified method to generate BTAGs in a decode unit of a processing system
IBM3 citations62
US5765221AJun 9, 1998
Method and system of addressing which minimize memory utilized to store logical addresses by storing high order bits within a register
IBM3 citations61
US7426631B2Sep 16, 2008
Methods and systems for storing branch information in an address table of a processor
IBM2 citations59
US7475223B2Jan 6, 2009
Fetch-side instruction dispatch group formation
IBM0 citations52
US7412620B2Aug 12, 2008
Method for testing ability to recover from cache directory errors
IBM1 citations52
US7984280B2Jul 19, 2011
Storing branch information in an address table of a processor
IBM0 citations48