Inventor

GOEL ARNAV

US23 patents

⚠️ This page may combine multiple inventors who share the name “GOEL ARNAV”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GOEL ARNAV

SAMBANOVA SYSTEMS INC

Inter-node buffer-based streaming for reconfigurable processor-as-a-service (RPaaS)

Runtime execution of functions across reconfigurable processor

Inter-processor execution of configuration files on reconfigurable processors using smart network interface controller (SmartNIC) buffers

Inter-node execution of configuration files on reconfigurable processors using smart network interface controller (smartnic) buffers

Runtime execution of configuration files on reconfigurable processors with varying configuration granularity

Intra-node buffer-based streaming for reconfigurable processor-as-a-service (RPaaS)

Inter-node execution of configuration files on reconfigurable processors using network interface controller (NIC) buffers

Data transfer between accessible memories of multiple processors incorporated in coarse-grained reconfigurable (CGR) architecture within heterogeneous processing system using one memory to memory transfer operation

Runtime virtualization of reconfigurable data flow resources

Time-multiplexed use of reconfigurable hardware

Runtime virtualization of reconfigurable data flow resources

System of heterogeneous reconfigurable processors for the data-parallel execution of applications

System for executing an application on heterogeneous reconfigurable processors

Method and apparatus for data transfer between accessible memories of multiple processors in a heterogeneous processing system using two memory to memory transfer operations

Load balancing system for the execution of applications on reconfigurable processors

Method and apparatus for selecting data access method in a heterogeneous processing system with multiple processors

Method and apparatus for data access in a heterogeneous processing system with multiple processors using memory extension operation

Debugging framework for a reconfigurable data processor

Intelligent graph execution and orchestration engine for a reconfigurable data processor

System and method for user interactive pipelining of a computing application

Direct access to reconfigurable processor memory

CISCO TECH INC

Fast receive re-convergence of multi-pod multi-destination traffic in response to local disruptions

Fast receive re-convergence of multi-pod multi-destination traffic in response to local disruptions