P

Inventor

PRANATHARTHIHARAN BALASUBRAMANIAN S

US25 patents
⚠️ This page may combine multiple inventors who share the name “PRANATHARTHIHARAN BALASUBRAMANIAN S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IBM

21 patents
US9660028B1May 23, 2017

Stacked transistors with different channel widths

IBM93 citations99
US9741823B1Aug 22, 2017

Fin cut during replacement gate formation

IBM22 citations94
US9721848B1Aug 1, 2017

Cutting fins and gates in CMOS devices

IBM32 citations94
US9397006B1Jul 19, 2016

Co-integration of different fin pitches for logic and analog devices

IBM25 citations94
US10242981B2Mar 26, 2019

Fin cut during replacement gate formation

IBM5 citations84
US9634110B2Apr 25, 2017

POC process flow for conformal recess fill

IBM4 citations84
US9576954B1Feb 21, 2017

POC process flow for conformal recess fill

IBM8 citations84
US9406767B1Aug 2, 2016

POC process flow for conformal recess fill

IBM6 citations84
US9275901B1Mar 1, 2016

Semiconductor device having reduced contact resistance

IBM6 citations84
US11894436B2Feb 6, 2024

Gate-all-around monolithic stacked field effect transistors having multiple threshold voltages

IBM3 citations75
US12268031B2Apr 1, 2025

Backside power rails and power distribution network for density scaling

IBM2 citations74
US10354921B2Jul 16, 2019

Stacked transistors with different channel widths

IBM2 citations73
US10224326B2Mar 5, 2019

Fin cut during replacement gate formation

IBM3 citations73
US9882028B2Jan 30, 2018

Pitch split patterning for semiconductor devices

IBM4 citations73
US12278237B2Apr 15, 2025

Stacked FETS with non-shared work function metals

IBM1 citations64
US12563980B2Feb 24, 2026

Selective deposition and cross-linking of polymeric dielectric material

IBM0 citations62
US12476144B2Nov 18, 2025

Etch back and film profile shaping of selective dielectric deposition

IBM0 citations62
US9911823B2Mar 6, 2018

POC process flow for conformal recess fill

IBM0 citations52
US9627322B2Apr 18, 2017

Semiconductor device having reduced contact resistance

IBM0 citations52
US12563817B2Feb 24, 2026

Integrating gate-cuts and single diffusion break isolation post-RMG using low-temperature protective liners

IBM0 citations51
US10347749B2Jul 9, 2019

Reducing bending in parallel structures in semiconductor fabrication

IBM0 citations42

TESSERA LLC

1 patent

APPLIED MATERIALS INC

1 patent

ADEIA SEMICONDUCTOR SOLUTIONS LLC

1 patent

TESSERA INC

1 patent