Inventor

FAROOQ MUKTA G

US189 patents

⚠️ This page may combine multiple inventors who share the name “FAROOQ MUKTA G”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

FAROOQ MUKTA G

IBM

Metal to metal bonding for stacked (3D) integrated circuits

Using crack arrestor for inhibiting damage from dicing and chip packaging interaction failures in back end of line structures

Vertical metal-insulator-metal (MIM) capacitor using gate stack, gate spacer and contact via

Single-melt enhanced reliability solder element interconnect

Structure for implementing secure multichip modules for encryption applications

Wire bonding personalization and discrete component attachment on wirebond pads

Techniques for forming interconnects

Structure and method for producing multiple size interconnections

Method and structure for implementing secure multichip modules for encryption applications

Fluidic cooling systems and methods for electronic components

Rework methods for lead BGA/CGA

Solder hierarchy for lead free solder joint

Structure and method for lead free solder electronic package interconnections

Thru-silicon-via structures

Structure and method for making crack stop for 3D integrated circuits

Simultaneously forming a through silicon via and a deep trench structure

Front side wafer ID processing

Fluorine depleted adhesion layer for metal interconnect structure

Underbump metallurgy for enhanced electromigration resistance

3D integration structure and method using bonded metal planes

Method and structure to reduce cracking in flip chip underfill

Method for forming C4 connections on integrated circuit chips and the resulting devices

Method and structure for implementing secure multichip modules for encryption applications

Method and structure for eliminating aluminum terminal pad material in semiconductor devices

Semiconductor module with improved interposer structure and method for forming the same

Method for separating electronic component from organic board

FAROOQ MUKTA G

Bonded structure employing metal semiconductor alloy bonding

Three dimensional integrated circuit integration using alignment via/dielectric bonding first and through via formation last

Method of making 3D integrated circuits

3D integrated circuit device fabrication with precisely controllable substrate removal

Metal-contamination-free through-substrate via structure

Soft error rate mitigation by interconnect structure

Three dimensional integrated circuit integration using dielectric bonding first and through via formation last

Structure and method for making crack stop for 3D integrated circuits

3-D integration using multi stage vias

Bonded structure with enhanced adhesion strength

TSV pillar as an interconnecting structure

3D integrated circuits structure

Alignment marks to enable 3D integration

3D integrated circuit device having lower-cost active circuitry layers stacked before higher-cost active circuitry layer

3D integrated circuit device fabrication using interface wafer as permanent carrier

Method of forming a multi-chip stacked structure including a thin interposer chip having a face-to-back bonding with another chip

VOLANT RICHARD P

Method of fabricating coaxial through-silicon via

Coaxial through-silicon via

Method and structure of forming backside through silicon via connections

GLOBALFOUNDRIES INC

Thru-silicon-via structures

SOI wafers with buried dielectric layers to prevent Cu diffusion

LANE MICHAEL W

Structure for inhibiting back end of line damage from dicing and chip packaging interaction failures

CHENG KANGGUO

Method for simultaneously forming a through silicon via and a deep trench structure

ANDRY PAUL S

Optimized annular copper TSV