Inventor

ABDALLAH MOHAMMAD A

US37 patents

⚠️ This page may combine multiple inventors who share the name “ABDALLAH MOHAMMAD A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ABDALLAH MOHAMMAD A

INTEL CORP

Method and apparatus for computing a sum of packed data elements using SIMD multiply circuitry

Memory access latency hiding with hint buffer

Method and apparatus for floating point operations and format conversion operations

Hardware predication for conditional instruction path branching

Method and apparatus for computing a packed absolute differences with plurality of sign bits using SIMD add circuitry

Executing partial-width packed data instructions

Executing partial-width packed data instructions

Processor for computing a packed sum of absolute differences and packed multiply-add

Hardware predication for conditional instruction path branching

3X adder

Cache storing data fetched by address calculating load instruction with label used as associated name for consuming instruction to refer

Apparatus and method for processing an instruction matrix specifying parallel and dependent operations

Pixel span depth buffer

Method and apparatus for nearest potential store tagging

Disambiguation-free out of order load store queue

Reordered speculative instruction sequences with a disambiguation-free out of order load store queue

Method for implementing a reduced size register view data structure in a microprocessor

System and method for prefetching data into a cache based on miss distance

System and method for prefetching data into a cache based on miss distance

Instruction definition to implement load store reordering and optimization

Determining branch targets for guest branch instructions executed in native address space

Apparatus and method for processing an instruction matrix specifying parallel and dependent operations

Method and apparatus for guest return address stack emulation supporting speculation

Method and apparatus to allow early dependency resolution and data forwarding in a microprocessor

Method and apparatus for sorting elements in hardware structures

Method and apparatus for guest return address stack emulation supporting speculation

Virtual load store queue having a dynamic dispatch window with a unified structure

Cache storing data fetched by address calculating load instruction with label used as associated name for consuming instruction to refer

Method and apparatus to increase the speed of the load access and data return speed path using early lower address bits

Apparatus and method for processing an instruction matrix specifying parallel and dependent operations

Method and apparatus for sorting elements in hardware structures

Regulating a timing between a strobe signal and a data signal

SOFT MACHINES INC

Processor executing super instruction matrix with register file configurable for single or multiple threads operations

Cache storing data fetched by address calculating load instruction with label used as associated name for consuming instruction to refer

Method and apparatus for sorting elements in hardware structures

ABDALLAH MOHAMMAD A

Parallel processing of a sequential program using hardware generated threads and their instruction groups executing on plural execution units and accessing register file segments using dependency inheritance vectors across multiple engines

Plural matrices of execution units for processing matrices of row dependent instructions in single clock cycle in super or separate mode