Inventor

GSCHWIND MICHAEL K

US509 patents

⚠️ This page may combine multiple inventors who share the name “GSCHWIND MICHAEL K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GSCHWIND MICHAEL K

IBM

Fine-grained instruction enablement at sub-function granularity based on an indicated subrange of registers

Prefix computer instruction for compatibly extending instruction functionality

Selection of an entry point of a function having multiple entry points

Method for compiling scalar code for a single instruction multiple data (SIMD) execution engine

Multi-addressable register file

Forwarding stored dara fetched for out-of-order load/read operation to over-taken operation read-accessing same memory location

Method and apparatus for implementing execution predicates in a computer processing system

Pipeline control for high-frequency pipelined designs

Selectively controlling use of extended mode features

Selectively controlling use of extended mode features

Synchronizing updates of page table status indicators and performing bulk operations

Relocation of instructions that use relative addressing

Transparent code patching including updating of address translation structures

Usage of TOC register as application register

Optimizing subroutine calls based on architecture level of called subroutine

Runtime management of TOC pointer save and restore commands

Runtime management of TOC pointer save and restore commands

Architectural mode configuration

Flushing speculative instruction processing

Selective suppression of instruction cache-related directory access

Global entry point and local entry point for callee function

Modify and execute sequential instruction facility and instructions therefor

Soft error detection for latches

Floating point only SIMD instruction set architecture including compare, select, Boolean, and alignment operations

Aligning precision converted vector data using mask indicating offset relative to element boundary corresponding to precision type

Method and apparatus for efficient performance monitoring of a large number of simultaneous events

Low complexity speculative multithreading system based on unmodified microprocessor core

Methods for renaming stack references to processor registers

Caller protected stack return address in a hardware managed stack architecture

Managing translations across multiple contexts using a TLB with entries directed to multiple privilege levels and to multiple types of address spaces

Method for garbage collection in heterogeneous multiprocessor systems

Processor with low overhead predictive supply voltage gating for leakage power reduction

Method and apparatus for aligning memory write data in a microprocessor

Method and apparatus for reordering memory operations along multiple execution paths in a processor

GSCHWIND MICHAEL K

Compiling scalar code for a single instruction multiple data (SIMD) execution engine

Prefix computer instruction for compatibily extending instruction functionality

Optimizing subroutine calls based on architecture level of called subroutine

Performing aggressive code optimization with an ability to rollback changes made by the aggressive optimizations

EICHENBERGER ALEXANDRE E

Matrix multiplication operations using pair-wise load and splat operations

Complex matrix multiplication operations with data pre-conditioning in a high performance computing architecture

Matrix multiplication operations with data pre-conditioning in a high performance computing architecture

Checkpointing in speculative versioning caches

GLOBALFOUNDRIES INC

Managing high-conflict cache lines in transactional memory computing environments

Multi-petascale highly efficient parallel supercomputer

BLANER BARTHOLOMEW

Method for predictive decoding of a load tagged pointer instruction

Structure for predictive decoding

ASAAD SAMEH

Multi-petascale highly efficient parallel supercomputer

BLAINEY ROBERT J

Linking code for an enhanced application binary interface (ABI) with decode time instruction optimization

CHER CHEN-YONG

Hybrid caching techniques and garbage collection using hybrid caching techniques

FLEISCHER BRUCE M

Soft error detection for latches