Inventor

DAVIS PAUL G

US54 patents

⚠️ This page may combine multiple inventors who share the name “DAVIS PAUL G”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DAVIS PAUL G

RAMBUS INC

System for a memory device having a power down mode and method

Method and apparatus for configuring access times of memory devices

Method and apparatus for fail-safe resynchronization with minimum latency

High performance cost optimized memory

Method and apparatus for two step memory write operations

DRAM core refresh with reduced spike current

Rambus DRAM (RDRAM) apparatus and method for performing refresh operations

Method and apparatus for initializing dynamic random access memory (DRAM) devices by levelizing a read domain

High performance cost optimized memory with delayed memory writes

Dram core refresh with reduced spike current

High performance cost optimized memory

DRAM core refresh with reduced spike current

DRAM core refresh with reduced spike current

Integrated circuit memory device with delayed write command processing

Integrated circuit memory device having write latency function

Memory system and method for two step memory write operations

Phase comparator capable of tolerating a non-50% duty-cycle clocks

Memory system and method for two step write operations

Synchronous memory device having a temperature register

Method and apparatus for adjusting the performance of a synchronous memory system

Memory system having delayed write timing

Integrated circuit memory device having delayed write timing based on read response time

Memory device having a configurable oscillator for refresh operation

Dram core refresh with reduced spike current

Apparatus and method for maximizing information transfers over limited interconnect resources

Memory device having a power down exit register

System and module including a memory device having a power down mode

Method and apparatus for fail-safe resynchronization with minimum latency

Apparatus and method for refreshing subsets of memory devices in a memory system

Integrated circuit memory device having delayed write timing based on read response time

Memory system and method for two step memory write operations

Integrated circuit memory device having delayed write capability

Memory Device Having a Configurable Oscillator for Refresh Operation

Apparatus and method for maximizing information transfers over limited interconnect resources

Apparatus and method for refreshing subsets of memory devices in a memory system

Memory system and method for two step memory write operations

Interface for a semiconductor memory device and method for controlling the interface

Memory device with delayed issuance of internal write command

Method and apparatus for adjusting the performance of a synchronous memory system

Method and apparatus for adjusting the performance of a synchronous memory system

DAVIS PAUL G

Portable travel exercise apparatus

Memory component having write operation with multiple time periods

Suspension training device

Serial peripheral interface

BARTH RICHARD M

Controlling DRAM at time DRAM ready to receive command when exiting power down

Method of operation of a memory device and system including initialization at a first frequency and operation at a second frequency and a power down exit mode

INTEL CORP

Memory device and system including a low power interface

MICROCHIP TECH INC

Method and apparatus for updating data in ROM using a CAM

GARLEPP BRUNO WERNER

Method and apparatus for adjusting the performance of a synchronous memory system

POWER STRAPS INC

Suspension training device