Inventor

JINDAL ANURAG

IN34 patents

⚠️ This page may combine multiple inventors who share the name “JINDAL ANURAG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

JINDAL ANURAG

MICRON TECHNOLOGY INC

Conductive interconnect structures incorporating negative thermal expansion materials and associated systems, devices, and methods

Conductive interconnect structures incorporating negative thermal expansion materials and associated systems, devices, and methods

Conductive interconnect structures incorporating negative thermal expansion materials and associated systems, devices, and methods

Conductive components and memory assemblies

Methods of exposing conductive Vias of semiconductor devices and related semiconductor devices

Conductive interconnect structures incorporating negative thermal expansion materials and associated systems, devices, and methods

Interconnect assemblies with through-silicon vias and stress-relief features

Conductive interconnect structures incorporating negative thermal expansion materials and associated systems, devices, and methods

Conductive components and memory assemblies

Conductive components and memory assemblies

Devices, systems and methods for manufacturing through-substrate vias and front-side structures

Devices, systems and methods for manufacturing through-substrate vias and front-side structures

Conductive interconnects

JINDAL ANURAG

Integrated circuit with increased fault coverage

Reset generation circuit for scan mode exit

Structural testing of integrated circuits

Multi-tiered semiconductor apparatuses including residual silicide in semiconductor tier

Method of generating test patterns for detecting small delay defects

Integrated circuit substrates comprising through-substrate vias and methods of forming through-substrate vias

NXP USA INC

Method and apparatus for digital only secure test mode entry

Identifying test coverage gaps for integrated circuit designs based on node testability and physical design data

System and method for facilitating built-in self-test of system-on-chips

Built in self test (BIST) for clock generation circuitry

FREESCALE SEMICONDUCTOR INC

Integrated circuit with scan chain having dual-edge triggered scannable flip flops and method of operating thereof

LBIST debug controller

Scan wrapper circuit for integrated circuit

SINGH NITIN

Data retention flip-flop

Method and system for logic built-in self-test

LI HONGQI

Methods of exposing conductive vias of semiconductor devices and associated structures

Post-tungsten CMP cleaning solution and method of using the same

AHMED NISAR

Built-in self test (BIST) with clock control

HUANG WAYNE H

Devices, systems, and methods related to planarizing semiconductor devices after forming openings

NANYA TECHNOLOGY CORP

Process of planarizing a wafer with a large step height and/or surface area features

BUSCH BRETT

Process of planarizing a wafer with a large step height and/or surface area features