Inventor

CHEN CHAO-CHENG

TW224 patents

⚠️ This page may combine multiple inventors who share the name “CHEN CHAO-CHENG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHEN CHAO-CHENG

TAIWAN SEMICONDUCTOR MFG

Multiple etch method for forming residue free patterned hard mask layer

Equal gate height control method for semiconductor device with different pattern densites

Fully dry post-via-etch cleaning method for a damascene process

Chemistry for etching organic low-k materials

Method for etching reliable small contact holes with improved profiles for semiconductor integrated circuits using a carbon doped hard mask

Hard mask method for forming chlorine containing plasma etched layer

Post via etch plasma treatment method for forming with attenuated lateral etching a residue free via through a silsesquioxane spin-on-glass (SOG) dielectric layer

Dual damascene process for carbon-based low-K materials

Plasma etch method for forming patterned oxygen containing plasma etchable layer

Method of dual damascene etching

Fluorocarbon polymer layer deposition predominant pre-etch plasma etch method for forming patterned silicon containing dielectric layer

Method of making a FinFET device

Fin shape for fin field-effect transistors and method of forming

Method for preventing photoresist poisoning

Process for forming an integrated contact or via

Method for forming residue free etched silicon layer

HCL in overetch with hard mask to improve metal line etching profile

VLSIC patterning process

Bottom rounding in shallow trench etching using a highly isotropic etching step

Achievement of top rounding in shallow trench etch

Etch recipe for embedded DRAM passivation with etch stopping layer scheme

Method of making a FinFET device

Method and apparatus for backside polymer reduction in dry-etch process

Chemistry for liner removal in a dual damascene process

High Q inductor with Cu damascene via/trench etching simultaneous module

Dual damascene process to reduce etch barrier thickness

Method for forming a shallow trench with tapered profile and round corners for the application of shallow trench isolation (STI)

Method of reducing a critical dimension of a semiconductor device

Process for improving copper fill integrity

Film stack and etching sequence for dual damascene

Method of forming a pattern

FinFETs and methods for forming the same

FinFET device structure and methods of making same

Patterning methodology for uniformity control

Contact or via hole structure with enlarged bottom critical dimension

TAIWAN SEMICONDUCTOR MFG CO LTD

Method and structure for metal gates

Gate spacers and methods of forming same

Method and structure for metal gates

FinFET device

Method of forming an integrated circuit using a patterned mask layer

FinFET device

Method of forming an integrated circuit using a patterned mask layer

Composite dummy gate with conformal polysilicon layer for FinFET device

Method of forming an integrated circuit using a patterned mask layer

Fin shape for fin field-effect transistors and method of forming

Equal gate height control method for semiconductor device with different pattern densites

LIAW JHON-JHY

Shallow trench isolation with improved structure and method of forming

HUANG YUAN-SHENG

Semiconductor integrated circuit with metal gate

Lin yu chao

Fin field effect transistors

HSIEH TZU-YEN

Method of forming an integrated circuit