Inventor
FENGER RUSSELL J
US37 patents
⚠️ This page may combine multiple inventors who share the name “FENGER RUSSELL J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
30 patentsUS6751659B1Jun 15, 2004
Distributing policy information in a communication network
INTEL CORP259 citations99
US6973488B1Dec 6, 2005
Providing policy information to a remote device
INTEL CORP112 citations98
US6601082B1Jul 29, 2003
System and method for managing actions provided by a network using a policy tree
INTEL CORP108 citations98
US5701476ADec 23, 1997
Method and apparatus for dynamically loading a driver routine in a computer memory
INTEL CORP114 citations98
US5832283ANov 3, 1998
Method and apparatus for providing unattended on-demand availability of a computer system
INTEL CORP148 citations97
US6065123AMay 16, 2000
Computer system with unattended on-demand availability
INTEL CORP99 citations96
US5902352AMay 11, 1999
Method and apparatus for task scheduling across multiple execution sessions
INTEL CORP139 citations96
US7818596B2Oct 19, 2010
Method and apparatus of power management of processor
INTEL CORP53 citations94
US6704319B1Mar 9, 2004
Up-tree topology trace for network route tracing
INTEL CORP16 citations93
US10317976B2Jun 11, 2019
Method, apparatus, and system for energy efficiency and energy conservation including power and performance balancing between multiple processing elements and/or a communication bus
INTEL CORP6 citations84
US7917789B2Mar 29, 2011
System and method for selecting optimal processor performance levels by using processor hardware feedback mechanisms
INTEL CORP15 citations83
US7340531B2Mar 4, 2008
Apparatus and method for data transfer
INTEL CORP11 citations81
US11106262B2Aug 31, 2021
Method, apparatus, and system for energy efficiency and energy conservation including power and performance balancing between multiple processing elements and/or a communication bus
INTEL CORP2 citations73
US9703352B2Jul 11, 2017
Method, apparatus, and system for energy efficiency and energy conservation including power and performance balancing between multiple processing elements and/or a communication bus
INTEL CORP2 citations73
US7646759B2Jan 12, 2010
Apparatus and method for configuring data plane behavior on network forwarding elements
INTEL CORP7 citations73
US11899599B2Feb 13, 2024
Apparatuses, methods, and systems for hardware control of processor performance levels
INTEL CORP2 citations72
US11182315B2Nov 23, 2021
Apparatuses, methods, and systems for hardware control of processor performance levels
INTEL CORP1 citations72
US10545793B2Jan 28, 2020
Thread scheduling using processing engine information
INTEL CORP3 citations72
US9727345B2Aug 8, 2017
Method for booting a heterogeneous system and presenting a symmetric core view
INTEL CORP3 citations72
US9639372B2May 2, 2017
Apparatus and method for heterogeneous processors mapping to virtual cores
INTEL CORP2 citations72
US9329900B2May 3, 2016
Hetergeneous processor apparatus and method
INTEL CORP6 citations72
US10372493B2Aug 6, 2019
Thread and/or virtual machine scheduling for cores with diverse capabilities
INTEL CORP4 citations71
US10162687B2Dec 25, 2018
Selective migration of workloads between heterogeneous compute elements based on evaluation of migration performance benefit and available energy and thermal budgets
INTEL CORP5 citations71
US8904205B2Dec 2, 2014
Increasing power efficiency of turbo mode operation in a processor
INTEL CORP4 citations71
US8683240B2Mar 25, 2014
Increasing power efficiency of turbo mode operation in a processor
INTEL CORP4 citations71
US10503550B2Dec 10, 2019
Dynamic performance biasing in a processor
INTEL CORP2 citations69
US12547564B2Feb 10, 2026
Apparatuses, methods, and systems for hardware control of processor performance levels
INTEL CORP0 citations62
US9448829B2Sep 20, 2016
Hetergeneous processor apparatus and method
INTEL CORP2 citations62
US11354213B2Jun 7, 2022
Utilization metrics for processing engines
INTEL CORP0 citations58
US7463638B2Dec 9, 2008
Up-tree topology trace for network route tracing
INTEL CORP1 citations52
SCHLUESSLER TRAVIS T
2 patentsUS8898494B2Nov 25, 2014
Power budgeting between a processing core, a graphics core, and a bus on an integrated circuit when a limit is reached
SCHLUESSLER TRAVIS T13 citations92
US9304570B2Apr 5, 2016
Method, apparatus, and system for energy efficiency and energy conservation including power and performance workload-based balancing between multiple processing elements
SCHLUESSLER TRAVIS T6 citations84