Inventor

JAYASENA NUWAN

US71 patents

⚠️ This page may combine multiple inventors who share the name “JAYASENA NUWAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

JAYASENA NUWAN

ADVANCED MICRO DEVICES INC

Method and apparatus for reducing TLB shootdown overheads in accelerator-based systems

Cache coherence for processing in memory

Processing device with address translation probing and methods

Light-weight cache coherence for data processors with limited data sharing

Circuit board with phase change material

Near-memory hardened compute blocks for configurable computing substrates

Method and systems of controlling memory-to-memory copy operations

Device and method for accelerating matrix multiply operations

Semi-sorting compression with encoding and decoding tables

Locality-aware and sharing-aware cache coherence for collections of processors

Compressing tags in software and hardware semi-sorted caches

Thermal aware data placement and compute dispatch in a memory system

Hardware-software collaborative address mapping scheme for efficient processing-in-memory systems

Hardware-software collaborative address mapping scheme for efficient processing-in-memory systems

Protecting host memory from access by untrusted accelerators

Memory operation encryption

Data processing system with decoupled data operations

Asynchronous cache flushing

System and method for coalesced multicast data transfers over memory interfaces

Memory page access counts based on page refresh

Allocation of resources when processing at memory level through memory request scheduling

Lightweight address translation for page migration and duplication

Approach for processing near-memory processing commands using near-memory register definition data

Approach for performing efficient memory operations using near-memory compute elements

Device and method for accelerating matrix multiply operations

System and method using hash table with a set of frequently-accessed buckets and a set of less frequently-accessed buckets

Implementing heterogeneous wavefronts on a graphics processing unit (GPU)

Error detection and correction in memory modules using programmable ECC engines

Using epoch counter values for controlling the retention of cache blocks in a cache

Approach for supporting memory-centric operations on cached data

Approach for reducing side effects of computation offload to memory

Circuit board with phase change material

Semi-sorting compression with encoding and decoding tables

Method and apparatus to support instruction replay for executing idempotent code in dependent processing in memory devices

Providing host-based error detection capabilities in a remote execution device

Command throughput in PIM-enabled memory using available data bus bandwidth

Memory access commands with near-memory address generation

Near-memory data reduction

Device and method for accelerating matrix multiply operations

Process isolation for a processor-in-memory (“PIM”) device

Virtual partitioning a processor-in-memory (“PIM”)

Partition and isolation of a processing-in-memory (PIM) device

Process isolation for a processor-in-memory (“PIM”) device

Dynamically coalescing atomic memory operations for memory-local computing

Control system and architecture for incorporating microelectromechanical (MEM) switches in fluid-based cooling of 3D integrated circuits

Memory allocation for processing-in-memory operations

HARTOG ROBERT SCOTT

Preemptive context switching of processes on ac accelerated processing device (APD) based on time quanta

Process device context switching

Preemptive context switching

ARORA MANISH

Distributed computing with phase change material thermal management