Inventor

CORDERO EDGAR R

US62 patents

⚠️ This page may combine multiple inventors who share the name “CORDERO EDGAR R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CORDERO EDGAR R

IBM

Programmable logic circuit using three-dimensional stacking techniques

System and method for computer memory with linked paths

Implementing ECC redundancy using reconfigurable logic blocks

Self monitoring and self repairing ECC

Flash memory scrub management

Memory margin management

Adjusting power management controls of a memory based on traffic

Switching a defective signal line with a spare signal line without shutting down the computer system

Volatile and non-volatile memory in a TSV module

Random access memory with pseudo-differential sensing

Method and apparatus to reduce bandwidth overhead of CRC protection on a memory channel

Reference voltage calibration in memory during runtime

Error correction for memory systems

Implementing DRAM refresh power optimization during long idle mode

Memory power management and data consolidation

Memory operation of paired memory devices

Switching a defective signal line with a spare signal line without shutting down the computer system

Method and apparatus to reduce bandwidth overhead of CRC protection on a memory channel

Implementing enhanced reliability of systems utilizing dual port DRAM

Reference voltage modification in a memory device

Real-time error debugging

Implementing DIMM air flow baffle

Implementing DIMM air flow baffle

Method and apparatus for cache memory data processing

Method and apparatus for cache memory data processing

Memory power management and data consolidation

System and method for computer memory with linked paths

Self monitoring and self repairing ECC

Memory power management and data consolidation

Prioritizing refreshes in a memory device

Reference voltage modification in a memory device

Prioritizing refreshes in a memory device

Accessing additional memory space with multiple processors

Accessing additional memory space with multiple processors

Memory operation of paired memory devices

Memory operation upon failure of one of two paired memory devices

Managing heterogeneous memory resource within a computing system

Auto-disabling DRAM error checking on threshold

Auto-disabling DRAM error checking on threshold

Implementing enhanced reliability of systems utilizing dual port DRAM

Implementing simultaneous read and write operations utilizing dual port DRAM

Implementing simultaneous read and write operations utilizing dual port DRAM

CORDERO EDGAR R

Three dimensional (3D) memory device sparing

Programmable logic circuit using three-dimensional stacking techniques

Implementing chip to chip calibration within a TSV stack

Requesting a memory space by a memory controller

Three dimensional(3D) memory device sparing

Implementing memory performance management and enhanced memory reliability accounting for thermal conditions

Implementing enhanced hardware assisted DRAM repair using a data register for DRAM repair selectively provided in a DRAM module

Implementing DRAM command timing adjustments to alleviate DRAM failures