Inventor
FIRSTENBERG MARK A
US4 patents
Patents
4 patentsUS4985825AJan 15, 1991
System for delaying processing of memory access exceptions until the execution stage of an instruction pipeline of a virtual memory system based digital computer
DIGITAL EQUIPMENT CORP128 citations97
US5142633AAug 25, 1992
Preprocessing implied specifiers in a pipelined processor
DIGITAL EQUIPMENT CORP57 citations95
US5167026ANov 24, 1992
Simultaneously or sequentially decoding multiple specifiers of a variable length pipeline instruction based on detection of modified value of specifier registers
DIGITAL EQUIPMENT CORP53 citations90
US5142631AAug 25, 1992
System for queuing individual read or write mask and generating respective composite mask for controlling access to general purpose register
DIGITAL EQUIPMENT CORP54 citations90