Inventor
SANGANERIA MAHESH K
US12 patents
⚠️ This page may combine multiple inventors who share the name “SANGANERIA MAHESH K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
NOVELLUS SYSTEMS INC
3 patentsUS7396759B1Jul 8, 2008
Protection of Cu damascene interconnects by formation of a self-aligned buffer layer
NOVELLUS SYSTEMS INC105 citations97
US8030777B1Oct 4, 2011
Protection of Cu damascene interconnects by formation of a self-aligned buffer layer
NOVELLUS SYSTEMS INC18 citations92
US6403501B1Jun 11, 2002
Method of controlling FSG deposition rate in an HDP reactor
NOVELLUS SYSTEMS INC13 citations68
UNIV NORTH CAROLINA STATE
3 patentsUS5242847ASep 7, 1993
Selective deposition of doped silion-germanium alloy on semiconductor substrate
UNIV NORTH CAROLINA STATE159 citations97
US5336903AAug 9, 1994
Selective deposition of doped silicon-germanium alloy on semiconductor substrate, and resulting structures
UNIV NORTH CAROLINA STATE55 citations94
US5439850AAug 8, 1995
Method for forming a layer of uniform thickness on a semiconductor wafer during rapid thermal processing
UNIV NORTH CAROLINA STATE16 citations66
MATTSON TECH INC
2 patentsLSI LOGIC CORP
2 patentsUS5895261AApr 20, 1999
Process for making integrated circuit structure comprising local area interconnects formed over semiconductor substrate by selective deposition on seed layer in patterned trench
LSI LOGIC CORP32 citations92
US5670425ASep 23, 1997
Process for making integrated circuit structure comprising local area interconnects formed over semiconductor substrate by selective deposition on seed layer in patterned trench
LSI LOGIC CORP41 citations92