Inventor

INOSHITA MINORU

US8 patents

⚠️ This page may combine multiple inventors who share the name “INOSHITA MINORU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BULL HN INFORMATION SYST

5 patents

US5649090AJul 15, 1997

Fault tolerant multiprocessor computer system

BULL HN INFORMATION SYST67 citations93

US6006309ADec 21, 1999

Information block transfer management in a multiprocessor computer system employing private caches for individual center processor units and a shared cache

BULL HN INFORMATION SYST18 citations82

US5829029AOct 27, 1998

Private cache miss and access management in a multiprocessor system with shared memory

BULL HN INFORMATION SYST17 citations82

US5963973AOct 5, 1999

Multiprocessor computer system incorporating method and apparatus for dynamically assigning ownership of changeable data

BULL HN INFORMATION SYST9 citations68

US5422837AJun 6, 1995

Apparatus for detecting differences between double precision results produced by dual processing units operating in parallel

BULL HN INFORMATION SYST4 citations60

HONEYWELL INF SYSTEMS

3 patents

US4558412ADec 10, 1985

Direct memory access revolving priority apparatus

HONEYWELL INF SYSTEMS27 citations89

US4240140ADec 16, 1980

CRT display terminal priority interrupt apparatus for generating vectored addresses

HONEYWELL INF SYSTEMS19 citations71

US4225942ASep 30, 1980

Daisy chaining of device interrupts in a cathode ray tube device

HONEYWELL INF SYSTEMS9 citations71