Inventor
QUAY STEPHEN THOMAS
US20 patents
Patents
20 patentsUS6347393B1Feb 12, 2002
Method and apparatus for performing buffer insertion with accurate gate and interconnect delay computation
IBM230 citations99
US6117182ASep 12, 2000
Optimum buffer placement for noise avoidance
IBM229 citations99
US7065730B2Jun 20, 2006
Porosity aware buffered steiner tree construction
IBM95 citations97
US6401234B1Jun 4, 2002
Method and system for re-routing interconnects within an integrated circuit design having blockages and bays
IBM132 citations95
US7299442B2Nov 20, 2007
Probabilistic congestion prediction with partial blockages
IBM19 citations92
US6044209AMar 28, 2000
Method and system for segmenting wires prior to buffer insertion
IBM33 citations92
US7127696B2Oct 24, 2006
Method and apparatus for generating steiner trees using simultaneous blockage avoidance, delay optimization and design density management
IBM26 citations91
US6591411B2Jul 8, 2003
Apparatus and method for determining buffered steiner trees for complex circuits
IBM30 citations91
US6360350B1Mar 19, 2002
Method and system for performing circuit analysis on an integrated-circuit design having design data available in different forms
IBM39 citations91
US6230302B1May 8, 2001
Method and system for performing timing analysis on an integrated circuit design
IBM20 citations91
US10831971B1Nov 10, 2020
Net layer promotion with swap capability in electronic design
IBM8 citations82
US6560752B1May 6, 2003
Apparatus and method for buffer library selection for use in buffer insertion
IBM16 citations82
US7676780B2Mar 9, 2010
Techniques for super fast buffer insertion
IBM6 citations74
US6898774B2May 24, 2005
Buffer insertion with adaptive blockage avoidance
IBM10 citations73
US7137081B2Nov 14, 2006
Method and apparatus for performing density-biased buffer insertion in an integrated circuit design
IBM10 citations72
US10839122B1Nov 17, 2020
Automatic layer trait generation and promotion cost computation
IBM3 citations71
US5991521ANov 23, 1999
Method and system of checking for open circuit connections within an integrated-circuit design represented by a hierarchical data structure
IBM8 citations71
US6915496B2Jul 5, 2005
Apparatus and method for incorporating driver sizing into buffer insertion using a delay penalty estimation technique
IBM10 citations70
US8386985B2Feb 26, 2013
Timing driven routing in integrated circuit design
IBM2 citations63
US7392493B2Jun 24, 2008
Techniques for super fast buffer insertion
IBM5 citations63