Inventor

SABDE JAGDISH

US21 patents

⚠️ This page may combine multiple inventors who share the name “SABDE JAGDISH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SABDE JAGDISH

SANDISK TECHNOLOGIES INC

Block and zone erase algorithm for memory

Non-volatile memory with multi-word line select for defect detection operations

Techniques for detecting broken word lines in non-volatile memories

Select gate defect detection

Techniques for detection and treating memory hole to local interconnect marginality defects

Word line look ahead read for word line to word line short detection

Methods to improve programming of slow cells

AC stress methods to screen out bit line defects

Stress patterns to detect shorts in three dimensional non-volatile memory

Current based detection and recording of memory hole-interconnect spacing defects

Adaptive multi-page programming methods and apparatus for non-volatile memory

SANDISK TECHNOLOGIES LLC

Multi-tier memory stack structure containing non-overlapping support pillar structures and method of making thereof

Erase stress and delta erase loop count methods for various fail modes in non-volatile memory

Techniques for determining local interconnect defects

NAND structure with tier select gate transistors

Determination of word line to word line shorts between adjacent blocks

Partial memory die

High-speed data path testing techniques for non-volatile memory

Determination of word line to word line shorts between adjacent blocks

AC stress mode to screen out word line to word line shorts

Partial memory die with inter-plane re-mapping